A4992 Datasheet, PDF (27/29 Pages) Allegro MicroSystems – Automotive Stepper Driver

A4992
Automotive Stepper Driver
The step rate is controlled by the timing of the serial interface.
It is the inverse of the step time, t_STEP , shown in figure 15. The
motor step only takes place when the STRn goes from low to
high when writing to the Run register. The motor step rate is
therefore determined by the timing of the rising edge of the STRn
input. The clock rate of the serial interface, defined by the fre-
quency of the SCK input, has no effect on the step rate.
Layout
The printed circuit board (PCB) should use a higher weight cop-
per thickness than a standard small signal or digital board. This
helps to reduce the impedance of the copper traces when conduct-
ing high currents. PCB traces carrying switching currents should
be as wide and short as possible to reduce the inductance of the
trace. This will help reduce any voltage transients caused by cur-
rent switching during PWM current control.
For optimum thermal performance, the exposed thermal pad on
the underside of the A4992 should be soldered directly onto the
board. A solid ground plane should be added to the opposite side
of the board and multiple vias through the board placed in the
area under the thermal pad.
Decoupling
All supplies should be decoupled with an electrolytic capaci-
tor in parallel with a ceramic capacitor. The ceramic capacitor
should have a value of 100 nF and should be placed as close as
possible to the associated supply and ground pins of the A4992.
The electrolytic capacitor connected to VBB should be rated to at
least 1.5 times the maximum voltage and selected to support the
maximum ripple current provided to the motor. The value of the
capacitor is unimportant but should be the lowest value with the
necessary ripple current capability.
The pump capacitor between CP1 and CP2, the pump storage
capacitor between VCP and VBB, and the compensation capaci-
tor between VREG and ground should be connected as close as
possible to the respective pins of the A4992.
Grounding
A star ground system, with the common star point located close
to the A4992 is recommended. On the 20-lead TSSOP package,
the reference ground, AGND (pin 6), and the power ground,
PGND (pin 9), must be connected together externally. The copper
ground plane located under the exposed thermal pad is typically
used as the star ground point.
Current Sense Resistor
To minimize inaccuracies caused by ground-trace IR drops in
sensing the output current level, the current-sense resistors ( R_Sx )
should have an independent ground return to the star ground
point. This path should be as short as possible. For low-value
sense resistors the IR drop in the PCB trace to the sense resis-
tor can be significant and should be taken into account. Surface
mount chip resistors are recommended to minimize contact
resistance and parasitic inductance. The value, R_S, of the sense
resistors is given by:
R_S
=
V_REF
16 × I_SMAX
There is no restriction on the value of R_S or V_REF , other than the
range of V_REF over which the output current precision is guar-
anteed. However, it is recommended that the value of V_REF be
kept as high as possible to improve the current accuracy. Table 7
provides increasing values of I_SMAX for suggested values of V_REF
and standard E96 values of R_S .
Table 7. Suggested Values
I_SMAX
(mA)
R_S
(mΩ)
V_REF
(V)
100
499
0.8
200
499
1.6
300
417
2.0
405
309
2.0
501
249
2.0
610
205
2.0
702
178
2.0
812
154
2.0
912
137
2.0
1008
124
2.0
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com