A8585 Datasheet, PDF (24/35 Pages) Allegro MicroSystems – Automotive AEC-Q100 qualified

A8585
Wide Input Voltage, 2 A Buck
Regulator Family with Low IQ Mode
ance and 20% to 30% of inductor saturation.
The saturation current of the inductor should be higher than the
peak current capability of the device. Ideally, for output short
circuit conditions, the inductor should not saturate given the high-
est pulse-by-pulse current limit at minimum duty cycle (I_LIM(0)),
4.0 A (max). This may be too costly. At the very least, the induc-
tor should not saturate given the peak operating current according
to the following equation:
I_PEAK
=
4.1 –
S_E × (V_OUT + V_f )
1.15 × f_SW × (V_IN(MAX)+
V_f )
(5)
where V_IN(MAX) is the maximum continuous input voltage, such
as 18 V (not a surge voltage, like 40 V).
∆V_OUT = ∆I_L × ESR_CO
+ ^{VIN – VOUT}
L_O
× ESL_CO
+
∆I_L
8 f_SWC_O
(7)
The type of output capacitors determines which terms of equa-
tion 7 are dominant. For ceramic output capacitors the ESR_CO
and ESL_CO are virtually zero, so the output voltage ripple will be
dominated by the third term of equation 7:
∆V_OUT
≤
∆I_L
8 f_SWC_O
(8)
Starting with equation 5 and subtracting half of the inductor
ripple current provides us with an interesting equation to predict
the typical DC load capability of the regulator at a given duty
cycle (D):
To reduce the voltage ripple of a design using ceramic output
capacitors simply: increase the total capacitance, reduce the
inductor current ripple (that is, increase the inductor value), or
increase the switching frequency.
I_OUT(DC)
≤
4.1 –
S_E × D
f_SW
–
V_OUT × (1 – D )
2 × f_SW × L_O
(6)
After an inductor is chosen it should be tested during output short
circuit conditions. The inductor current should be monitored
using a current probe. A good design should ensure the inductor
or the regulator are not damaged when the output is shorted to
ground at maximum input voltage and the highest expected ambi-
ent temperature.
Output Capacitors
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage, and they also store energy to
help maintain voltage regulation during a load transient. The
voltage rating of the output capacitors must support the output
voltage with sufficient design margin.
The output voltage ripple (ΔV_OUT ) is a function of the output
capacitor parameters: C_O , ESR_CO , and ESL_CO:
For electrolytic output capacitors the value of capacitance will be
relatively high, so the third term in equation 7 will be very small
and the output voltage ripple will be determined primarily by the
first two terms of equation 7:
∆V_OUT = ∆I_L × ESR_CO +
V_IN
L_O
× ESL_CO
(9)
To reduce the voltage ripple of a design using electrolytic output
capacitors simply: decrease the equivalent ESR_CO and ESL_CO
by using a high(er) quality capacitor, or add more capacitors in
parallel, or reduce the inductor current ripple (that is, increase the
inductor value).
The ESR of some electrolytic capacitors can be quite high so
Allegro recommends choosing a quality capacitor for which the
ESR or the total impedance is clearly documented in the capaci-
tor datasheet. Also, the ESR of electrolytic capacitors usually
increases significantly at cold ambients, as much as 10 X, which
increases the output voltage ripple and, in most cases, reduces the
stability of the system.
Allegro MicroSystems, LLC
24
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com