A4450 Datasheet, PDF(24/34 Page) Allegro MicroSystems – Buck-Boost Controller with Integrated Buck MOSFET

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A4450 Datasheet, PDF (24/34 Pages) Allegro MicroSystems – Buck-Boost Controller with Integrated Buck MOSFET

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A4450

Buck-Boost Controller

with Integrated Buck MOSFET

For a design with very low-ESR-type output capacitors (i.e.

ceramic or OSCON output capacitors), the ESR zero is usually

at a very high frequency, so it can be ignored. If the ESR zero

falls below or near the 0 dB crossover frequency of the system

(as is the case with electrolytic output capacitors), then it should

be cancelled by the pole formed by the CP capacitor and the RZ

resistor (identified and discussed later as fEA(p2)).

The feedback loop includes a feedback output voltage divider

(RFB1 and RFB2), the error amplifier (gmEA), and the compensa-

tion network (RZ, CZ, and CP). The transfer function of the feed-

back can be derived and simplified if RO(EA) â« RZ, and CZ â« CP.

In most cases, RO(EA) > 2 Mâ¦, 1 kâ¦ < RZ < 100 kâ¦, 220 pF <

CZ < 47 nF, and CP < 50 pF, so the following equations are very

accurate:

( )( ) feedback = GDC(EA) Ã

2Ï Ã fEA(z)

2Ï

Ã fEA(p1)

2Ï

Ã fEA(p2)

(22)

where

GDC(EA) is the DC gain of the feedback loop,

GDC(EA)

RFB2

RFB1 + RFB2

gmEA

RO(EA)

gmEA is the error amplifier transconductance (see EC table),

RO(EA) is the output resistance of the error amplifier (the small

output capacitance of the error amplifer is neglected), and

RO(EA) = AVOL / gmEA

AVOL is the error amplifier open-loop voltage gain (see EC

table),

fEA(z) is the low-frequency zero of the error amplifier compensa-

tion network,

fEA(z) =

2Ï Ã RZ Ã COUT

fEA(p1) is the low-frequency pole of the error amplifier compen-

sation network,

fEA(p1) =

2Ï Ã RO(EA) Ã CZ

fEA(p2) is the high-frequency pole of the error amplifier compen-

sation network,

fEA(p2) =

2Ï Ã RZ Ã CP

Placing fEA(z) just above fpower(p) will result in excellent phase

margin, but relatively slow transient recovery time.

The sum of power stage control-to-output response equation 21

and the feedback loop response equation 22, including error

amplifier, is the overall loop frequency response of the entire

system. The goal of compensation design is to shape the transfer

function of the overall loop to get a stable converter with the

desired loop gain and phase margin.

A Generalized Tuning Procedure

1. Choose the system bandwidth, fC, the frequency at which the

magnitude of the gain will cross 0 dB. Recommended values

for fC are fSW/20 < fC < fSW/7.5. A higher value of fC will gen-

erally provide a better transient response, while a lower value

of fC will be easier to obtain higher gain and phase margins.

2. Calculate the RZ resistor value to set the desired system

bandwidth (fC),

RFB1 + RFB2

2 Ã Ï Ã COUT

RZ = fC Ã

RFB2

Ã gmPOWER Ã gmEA

3. Calculate the dominant pole frequency of power stage

(fpower(p) ) formed by COUT and RL.

fpower(p)

2Ï

COUT

4. Calculate a range of values for the CZ capacitor and set the

compensation zero below the one fourth of the crossover

frequency fC,

2 Ã Ï Ã RZ Ã fC < CZ < 2 Ã Ï Ã RZ Ã 1.5 Ã fpower(p)

To maximize system stability (i.e. have the most gain mar-

gin), use a higher value of CZ. To optimize transient recovery

time at the expense of some phase margin, use a lower value

of CZ.

5. Calculate the frequency of the ESR zero (fESR(z)) formed by

the output capacitor(s).

fESR(z) =

2Ï Ã ESR Ã COUT

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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