A4985_12 Datasheet, PDF (20/22 Pages) Allegro MicroSystems – DMOS Microstepping Driver with Translator And Overcurrent Protection

A4985
DMOS Microstepping Driver with Translator
And Overcurrent Protection
ET Package, 32-Contact QFN with Exposed Thermal Pad
5.00 ±0.15
32
1
2
A
5.00 ±0.15
0.30
32
1.00
1
2
0.50
3.40 5.00
33X D
0.08 C
0.25±0.10
0.50 BSC
0.50±0.10
2
1
32
B
3.40
SEATING ^C
PLANE
0.90 ±0.10
1
3.40
5.00
C PCB Layout Reference View
For Reference Only; not for tooling use
(reference JEDEC MO-220VHHD-6)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
3.40
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference
IPC7351 QFN50P500X500X100-33V6M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, Inc.
20
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com