A4960 Datasheet, PDF (20/34 Pages) Allegro MicroSystems – The A4960 is a three-phase, sensorless, brushless DC (BLDC) motor controller for use with external N-channel power MOSFETs and is specifically designed for automotive applications.

A4960
Automotive, Sensorless BLDC Controller
Note that FF does not provide the same function as the general
fault output flag output on the DIAG pin (described above). The
fault output on the DIAG pin provides an indication that certain
types of faults are present and in some cases that the outputs have
been disabled. FF provides an indication that certain types of
faults have occurred since the last Diagnostic register reset and
the respective fault bit has been set.
Fault response action
For certain fault conditions, the response of the A4960 is deter-
mined by the state of the Enable Stop on Fault bit, ESF (Run
bit 6), as shown in table 2. When a short fault or overtemperature
condition is detected, if ESF is set to 1 the A4960 disables all
the gate drive outputs and coasts the motor. For short faults, this
disabled state will be latched until RESETN goes low, a serial
interface read is completed, or a power-on reset occurs. For
undervoltage fault conditions, the outputs will always be dis-
abled, regardless of the ESF bit setting.
When ESF is set to 0, although the general fault output flag
(DIAG pin) is still activated (low), the A4960 will not disrupt
normal operation under most conditions, and will therefore not
protect the motor or the drive circuit from damage. It is impera-
tive that the application master control circuit or other external
circuit takes any necessary action when a fault occurs, to prevent
damage to components.
Fault Mask register
Certain individual diagnostics can be disabled by setting the cor-
responding bit in the Mask register. If a bit is set to 1 in the Mask
Table 2: Fault Response Actions
Fault Description
Disable Outputs _Fault
ESF = 0 ESF = 1 ^Latched
No fault
No
No
n.a.
VDD Undervoltage
Yes*
Yes*
No
VREG Undervoltage
Yes*
Yes*
No
Bootstrap Undervoltage
Yes*
Yes*
Yes
Temperature Warning
No
No
No
Overtemperature
No
Yes*
No
Short to Ground
Short to Supply
Shorted Load
No
Yes*
Only
No
Yes*
when
No
Yes*
ESF = 1
* All gate drives low, all MOSFETs off
register, then the corresponding diagnostic will be completely
disabled. No fault states for the disabled diagnostic will be gener-
ated and neither the general fault output flag (DIAG pin) nor bits
in the Diagnostic register will be set.
The VDD Undervoltage and VREG Undervoltage faults can-
not be masked. V_DD undervoltage detection cannot be disabled
because the diagnostics and the output control depend on VDD
to operate correctly. V_REG undervoltage detection cannot be
disabled because it is safe to turn on the gate drive outputs only
when V_REG is at a sufficiently high voltage.
Note: Care must be taken when diagnostics are disabled to avoid
potentially damaging conditions.
Chip-level diagnostics
Parameters critical for safe operation of the A4960 and the
external MOSFETs are monitored. These include: maximum
chip temperature, minimum logic supply voltage, and the vari-
ous minimum voltages required to drive the external MOSFETs
(V_REG and each of the bootstrap voltages). Note that the main
supply voltage, V_BB , is not monitored for minimum voltage. This
is because the critical minimum voltages are generated by the
charge pumps internal to the A4960. When a fault is present, the
general fault output flag (DIAG pin) will be active (low).
Chip Fault States: Temperature Thresholds
Two temperature threshold actions are provided: a high tempera-
ture warning and an overtemperature shutdown.
• If the chip temperature rises above the Temperature Warning
Threshold, T_JW , the general fault output flag (DIAG pin) goes
low and the High Temperature Warning bit, TW (Diagnostic
bit 11) and the common Fault flag bit, FF (bit 15), are set to 1. No
other action is taken by the A4960. When the temperature drops
below T_JW by more than the hysteresis value, T_JWHys , the general
fault output flag (DIAG pin) goes high, but TW and FF remain
set in the Diagnostic register until a register reset.
• If the chip temperature rises above the Overtemperature Thresh-
old, T_JF , the general fault output flag (DIAG pin) goes low and
the overtemperature bit, TS (Diagnostic bit 10) and the common
Fault flag bit, FF (bit 15), are set to 1. When ESF (Run bit 6) is
set to 1, if an overtemperature is detected, all gate drive outputs
will be disabled automatically. If an overtemperature condition
occurs when ESF is set to 0, then no circuitry will be disabled
and action must be taken by the user to limit the power dissipa-
Allegro MicroSystems, Inc.
20
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com