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A4407 Datasheet, PDF (20/29 Pages) Allegro MicroSystems – The A4407 is an automotive power management IC that uses a 2.2 MHz constant on-time (COT) buck pre-regulator to supply a 5 V linear regulator, a 5 V tracking/protected linear regulator,
A4407
2.2 MHz Constant On-Time Buck Regulator
With Two External and Two Internal Linear Regulators
Worst-case ripple current occurs at maximum supply voltage.
After calculating the duty cycle for this condition, the ripple cur-
rent can be calculated:
D
=
VREG +
VIN(max)
Vf +
+ Vf
(RSENSE × Ipeak)
– (RDS(on) × Ipeak)
(11)
Using the duty cycle, the inductor value can be calculated using
the formula below:
L=
VIN –VREG
Iripple
1
× D × fSW (min)
(12)
Where Iripple is 25% of the maximum load current, and fSW(min)
is the minimum switching frequency, nominal frequency minus
25%. Continuing the example used above (using equation 9), a
1 A converter with a supply voltage of 13.5 V is the design objec-
tive. Assume the supply voltage can vary by ±10%, the output
voltage is 5.45 V, Vf is 0.5 V, VSENSE is 0.20, and the target fre-
quency is 2.2 MHz. Using equation 11, the duty cycle is calcu-
lated to be 36.45%. Assume the worst-case frequency is 2.2 MHz
minus 20%, or 1.76 MHz. Using these numbers in equation 12
shows that the minimum inductance for this converter is 9.6 μH.
Output Capacitor
The buck converter is designed to operate with a low-ESR
ceramic output capacitor. When choosing a ceramic capacitor,
make sure the rated voltage is at least 3 times the maximum
output voltage of the converter. This is because the capacitance of
a ceramic decreases the closer it is operated to its rated voltage. It
is recommended that the output be decoupled with a 10 μF, 16 V,
X7R ceramic capacitor. Larger capacitance may be required on
the outputs if load surges dramatically influence the output volt-
age.
Output voltage ripple is determined by the output capacitance;
and the effects of ESR and ESL can be ignored, assuming recom-
mended layout techniques are followed. The output voltage ripple
is approximated by:
Vripple = Iripple / (8 × fsw × COUT)
(13)
Input Capacitor
The value of the input capacitance affects the amount of cur-
rent ripple on the input. This current ripple is usually the source
of supply-side EMI. The amount of interference depends on the
impedance from the input capacitor and the bulk capacitance
located on the supply bus. In addition to the two 4.7 μF capaci-
tors, placing a small 0.1 μF ceramic capacitor very close to the
input supply pin helps reduce EMI effects. The small capacitor
helps reduce the very high frequency transient currents on the
supply line.
Non-Synchronous Diode
The non-synchronous diode (DBUCK in the Functional Block dia-
gram) conducts the current during the off-time. A Schottky diode
is required to minimize the forward drop and switching losses. In
order to size the diode correctly, it is necessary to find the aver-
age diode conduction current using the following formula:
ID(avg) = I load × (1 – D(min ))
(14)
where D(min) is the minimum duty cycle, defined as:
D(min ) = (VREG + Vf ) / (VIN + Vf )
(15)
where VIN is the maximum input voltage and Vf is the maximum
forward voltage of the diode.
The average power dissipation in the diode is:
PDBUCK(avg) = IBUCK(avg) × D(min ) × Vf
(16)
The power dissipation in the sense resistor must also be consid-
ered using I2R and the minimum duty cycle.
External MOSFET Selections
To choose an external MOSFET for the 3.3 V or for the
1.2 V/1.5 V/1.8 V linear regulator, consider: the maximum drain-
to-source voltage, VDS , the maximum continuous drain current,
ID , the threshold voltage, VGSTH , the on-resistance (RDS(on)(FET)),
and the thermal resistance (RθJC(FET)).
Allegro MicroSystems, Inc.
20
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com