5841 Datasheet, PDF (2/8 Pages) Allegro MicroSystems – BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS

5841 AND 5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
CLOCK 2
SERIAL
DATA IN
3
LOGIC
GROUND ⁴
FUNCTIONAL BLOCK DIAGRAM
(‘A’ Package Shown)
V_DD
5 ^LOGIC
SUPPLY
SERIAL-PARALLEL SHIFT REGISTER
6
SERIAL
DATA OUT
LATCHES
7 _STROBE
8
OUTPUT ENABLE
(ACTIVE LOW)
MOS
BIPOLAR
18
17
16
15
14
13
12
11
10
OUT ₁ OUT ₂ OUT ₃ OUT ₄ OUT ₅ OUT ₆ OUT ₇ OUT ₈ K
SUB
1
POWER
GROUND
9
Dwg. FP-013-2
A5841SLW
& A5842SLW
POWER
GROUND
1
SUB
CLOCK 2 CLK
SERIAL
DATA IN
3
GROUND 4
LOGIC SUPPLY 5 VDD
SERIAL
DATA OUT
6
STROBE 7 ST
OUTPUT
ENABLE
POWER
GROUND
NO
CONNECT.
8 _OE
9
SUB
10 NC
20 OUT1
19 OUT2
18 OUT ₃
17 OUT₄
16 OUT₅
15 OUT ₆
14 OUT₇
13 OUT ₈
12 K
NO
NC 11 _CONNECT.
Dwg. PP-029-3
2.5
18-PIN DIP, RθJA = 60°C/W
2.0
20-LEAD SOIC, RθJA = 70°C/W
18-LEAD SOIC, RθJA = 80°C/W
1.5
1.0
0.5
0
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GP-022-4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Copyright © 1985, 2000 Allegro MicroSystems, Inc.