A3921 Datasheet, PDF (15/21 Pages) Allegro MicroSystems – Automotive Full Bridge MOSFET Driver

A3921
Automotive Full Bridge MOSFET Driver
For R_DEAD values between 3 kΩ and 240 kΩ, at 25°C the nomi-
nal value of t_DEAD in ns can be approximated by:
7200
t_DEAD(nom) _{= 50 + 1.2 + (200 / RDEAD)}
, ₍₁₎
where R_DEAD is in kΩ. Greatest accuracy is obtained for values
of R_DEAD between 6 and 60 kΩ, which are shown in figure 3.
The I_DEAD current can be estimated by:
1.2
I_{DEAD = RDEAD} .
(2)
The maximum dead time, 6 μs typical, can be set by connecting
the RDEAD pin directly to the V5 pin.
PWML=0). This effectively short-circuits the back EMF of the
motor, creating a breaking torque.
During braking, the load current can be approximated by:
I_BRAKE
=
V_BEMF
R_L
,
(3)
where V_BEMF is the voltage generated by the motor and R_L is the
resistance of the phase winding.
Care must be taken during braking to ensure that maximum rat-
ings of the power FETs are not exceeded. Dynamic braking is
equivalent to slow decay with synchronous rectification.
The choice of power FET and external series gate resistance
determine the selection of the dead-time resistor, R_DEAD. The
dead time should be long enough to ensure that one FET in a
phase has stopped conducting before the complementary FET
starts conducting. This should also take into account the tolerance
and variation of the FET gate capacitance, the series gate resis-
tance, and the on-resistance of the A3921 internal drives.
Dead time will be present only if the on-command for one FET
occurs within t_DEAD after the off-command for its complementary
FET. In the case where one side of a phase drive is permanently
off, for example when using diode rectification with slow decay,
then the dead time will not occur. In this case the gate drive will
turn on within the specified propagation delay after the corre-
sponding phase input goes high. (Refer to the Gate Drive Timing
diagrams.)
Bootstrap Capacitor Selection
The bootstrap capacitors, C_BOOTx, must be correctly selected to
ensure proper operation of the A3921. If the capacitances are too
high, time will be wasted charging the capacitor, resulting in a
limit on the maximum duty cycle and the PWM frequency. If the
capacitances are too low, there can be a large voltage drop at the
time the charge is transferred from C_BOOTx to the FET gate, due
to charge sharing.
To keep this voltage drop small, the charge in the bootstrap
capacitor, Q_BOOT, should be much larger than the charge required
by the gate of the FET, Q_GATE. A factor of 20 is a reasonable
value, and the following formula can be used to calculate the
value for C_BOOT :
Q_{BOOT =} C_BOOT × V_BOOT = Q_GATE × 20 ,
Fault Blank Time
To avoid false short fault detection, the output from the V_DS
monitor for any FET is ignored when that FET is off and for a
period of time after it is turned on. This period of time is the fault
blank time. Its length is the dead time, t_DEAD , plus an additional
period of time that compensates for the delay in the V_DS moni-
tors. This additional delay is typically 300 to 600 ns.
Braking
The A3921 can be used to perform dynamic braking either by
forcing all low-side FETs on and all high-side FETs off (SR=1,
PWMH=0, and PWML=1) or conversely by forcing all low-
side FETs off and all high-side FETs on (SR=1, PWMH=1, and
therefore:
C_BOOT
=
Q_GATE × 20
V_BOOT
,
(4)
where V_BOOT is the voltage across the bootstrap capacitor.
The voltage drop across the bootstrap capacitor as the FET is
being turned on, ∆V , can be approximated by:
∆V _≈ ^{QGATE .}
C_BOOT
(5)
So, for a factor of 20, ∆V would be approximately 5% of V_BOOT .
The maximum voltage across the bootstrap capacitor under
normal operating conditions is V_REG(max). However, in some
circumstances the voltage may transiently reach 18 V, the clamp
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Worcester, Massachusetts 01615-0036 U.S.A.
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