A8904SLB Datasheet, PDF (14/18 Pages) Allegro MicroSystems – 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING

8904
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Functional Description (cont’d)
D28 - Programs the transconductance gain. LOW = 500 mA/V,
HIGH = 250 mA/V.
Reset. When the RESET terminal is pulled low, all the
serial port bits are reset to LOW and the part operates in sleep
mode.
Undervoltage lockout, V_DD. When an undervoltage
condition occurs, all the serial port bits are reset to LOW and the
part operates in sleep mode.
Charge pump. The charge pump is required to provide a
voltage rail above the load supply for driving the high-side
DMOS gates. In addition the charge pump supply capacitor,
C_RES, also powers the brake control circuit during power-down
conditions. C_RES should be 220 nF.
Braking. A dynamic braking feature of the A8904 shorts
the three motor windings to ground. This is accomplished by
turning the three source drivers OFF and the three sink drivers
ON. Activation of the brake can be implemented through the
BRAKE input or through the D2 bit in the serial port.
During braking, the motor is effectively acting as three sine-
wave voltage generators, 120° out of phase, where the voltage
developed by each of the windings is proportional to the motor
speed and constant. The current through any sink driver is
simply the generated voltage divided by the center tap to OUT
resistance plus the sink driver resistance. As the motor tends to
slow during the braking process, both the generated voltage and
the corresponding current decreases.
When selecting a motor to use where braking will be
applied, it is important to characterize the application to ensure
that when braking is applied, the peak current in the sink drivers
does not exceed 3A and the period from the peak current to the
maximum current limit of the drivers does not exceed 800 ms.
Another consideration is the thermals of the solution, where
repeated spin-up followed by brake cycles could cause excessive
junction temperatures.
The supply voltage for the brake circuit is derived from the
charge pump supply capacitor, C_RES. With C_RES chosen to be
220 nF, the brake circuit will function for at least 100 ms after a
power failure.
In certain applications such as disk drives, it is desirable to
include a brake delay to allow sensitive circuitry such as the disk
head to retract before activating the spindle motor brake. The
brake delay can be simply implemented by using an external RC
and diode to control the brake terminal.
FAULT
BRAKE
V _FAULT – V _D
BRAKE
ACTIVATED
CB
RB
t _BRK
V _BRK
Dwg. OP-004
The brake delay can be set using the equation:
t_BRK = –R_BC_B x ln (V_BRK / [V_FAULT – V_D]).
Once the brake is activated, the three sink drivers will
remain active until the supply rails fall below the operating
range. It is recommended that the part is reset before restarting.
Centertap. It is recommended that the centertap connec-
tion of the motor be connected to the CENTERTAP terminal. If
the centertap of the motor is not connected to the CENTERTAP
terminal, the A8904 internally emulates the centertap voltage of
the motor through a series of 10 kΩ resistors connected between
each output and CENTERTAP. This technique does not provide
ideal commutation points.
External component selection. All capacitors should
be rated to at least 25 V and the dielectric should be X7R, apart
from the start-up capacitor C_ST, which can be Z5U dielectric or
equivalent and the input capacitor C_filter, which should be an
electrolytic type of value greater than 100 µF, 35 V, I_ripple > 100
mA. If the solution experiences ambient temperatures of greater
than 70°C then C_filter should be rated for 105°C.
All resistors are at least 1/8 W and have a tolerance of ±5%.
In noise-sensitive systems where electromagnetic interfer-
ence is an issue, or to stabilize the current waveforms with
certain motors, it may be necessary to add RC snubbers across
the motor windings as shown in the application circuit on the
next page. The A8904 solution should be relatively noise
immune from the effects of switching voltage spikes etc. if the
correct watchdog capacitor has been selected for optimum
blanking and good layout practices are implemented.
At the range of operating frequencies that the current pulses
are drawn out of the load supply, it is the capacitance reactance
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