A8438_06 Datasheet, PDF (14/15 Pages) Allegro MicroSystems – Photoflash Capacitor Charger with IGBT Driver

A8438
Photoflash Capacitor Charger with IGBT Driver
Adjusting Output Voltage
The A8438 senses output voltage during switch off-time. This
allows the voltage divider network, R1 through R3 (see figure
6), to be connected at the anode of the high voltage output diode,
D1, eliminating power loss due to the feedback network when
charging is complete. The output voltage can be adjusted by
selecting proper values of the voltage divider resistors. Use the
following equation to calculate values for Rx (Ω):
R₁ + R_{2 =} V_{OUT − 1 .}
(4)
R₃
V_FB
R1 and R2 together need to have a breakdown voltage of at
least 300 V. A typical 1206 surface mount resistor has a 150 V
breakdown voltage rating. It is recommended that R1 and R2
have similar values to ensure an even voltage stress between
them. Recommended values are:
R1 = R2 = 150 kΩ (1206)
R3 = 1.2 kΩ (0603)
which together yield a stop voltage of 303 V.
Using higher resistance values for R1, R2, and R3 does not
offer significant efficiency improvement, because the power loss
of the feedback network occurs mainly during switch off-time,
and because the off-time is only a small fraction of each charging
cycle.
Output Diode Selection
Choose the rectifying diode(s), D1, to have small parasitic
capacitance (short reverse recovery time) while satisfying the
reverse voltage and forward current requirements.
The peak reverse voltage of the diode, V_{D_Peak} , occurs when the
internal MOSFET switch is closed, and the primary-side current
starts to ramp-up. It can be calculated as:
V_{D_} = _Peak V_OUT + N ×V_BATT .
(5)
The peak current of the rectifying diode, ID_Peak, is calculated
as :
/ ^I_{D_Peak} ^{= I}Primary_Peak ^{N .}
(6)
Input Capacitor Selection
Ceramic capacitors with X5R or X7R dielectrics are recom-
mended for the input capacitor, C2. It should be rated at least
4.7 μF / 6.3 V to decouple the battery input, V_BATT , at the primary
of the transformer. When using a separate bias, V_BIAS , for the
A8438 VIN supply, connect at least a 0.1 μF / 6.3 V bypass
capacitor to the VIN pin.
Layout Guidelines
Key to a good layout for the photoflash capacitor charger circuit
is to keep the parasitics minimized on the power switch loop
(transformer primary side) and the rectifier loop (secondary side).
Use short, thick traces for connections to the transformer primary
and SW pin.
Output voltage sensing circuit elements must be kept away from
switching nodes such as SW pin. Make sure that there is no GND
plane underneath R1 and R2, because parasitic capacitance to
ground will affect sensing accuracy. It is important that the ¯D¯¯O¯
¯N¯¯E¯ signal trace be routed away from the transformer and other
switching traces, in order to minimize noise pickup. In addition,
high voltage isolation rules must be followed carefully to avoid
breakdown failure of the circuit board.
Recommended Components Table
Component
Rating
C1 Input Capacitor 0.1 μF, ± 10%, 16 V X7R ceramic capacitor (0603)
C2 Input Capacitor 4.7 μF, ± 10%, 10 V, X5R ceramic capacitor (0805)
COUT Photoflash
Capacitor
330 V, 100 μF (or 19 to 180 μF)
Part Number
GRM188R71C104KA01D
LMK212BJ475KG
EPH-331ELL101B131S
D1, Output Diode
2 x 250 V, 225 mA, 5 pF
2 x 300 V, 225 mA, 5 pF
R1, R2, FB Resistors 150 kΩ, ¹/₄ W ± 1% (1206)
R3, FB Resistor
1.20 kΩ ¹/₁₀ W ± 1% (0603)
1:10, L_Primary = 10.8 μH, for I_LIM = 1.6 or 1.8 A
1:10.4, L_Primary = 4.7 μH, for I_LIM = 2.0 A
T1, Transformer
1:10, L_Primary = 8 μH, for I_LIM = 2.0 A
1:10, L_Primary = 7.4 μH, for I_LIM = 2.0 A
1:10, L_Primary = 14 μH, for I_LIM = 2.0 A
BAV23S
GSD2004S
9C12063A1503FKHFT
9T06031A1201FBHFT
ST-532517A
LDT565630T-041
DCT5EPL-UxxS002
T-16-103A
T-15-154M
Source
Murata
Taiyo Yuden
Chemi-Con
Philips Semiconductor,
Fairchild Semiconductor
Vishay
Yageo
Yageo
Asatech
TDK
TDK
Tokyo Coil Engineering
Tokyo Coil Engineering
Allegro MicroSystems, Inc.
14
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com