A5985 Datasheet, PDF (12/26 Pages) Allegro MicroSystems – DMOS Microstepping Driver with Translator

A5985
DMOS Microstepping Driver with Translator
And Overcurrent Protection
Step Input (STEP)
Blanking
A low-to-high transition on the STEP input sequences the transla-
tor and advances the motor one increment. The translator controls
the input to the DACs and the direction of current flow in each
winding. The size of the increment is determined by the combined
state of the MSx inputs.
Direction Input (DIR)
This function blanks the output of the current sense comparators
when the outputs are switched by the internal current control
circuitry. The comparator outputs are blanked to prevent false
overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, t_BLANK (µs), is approximately
This determines the direction of rotation of the motor. Setting
to logic high and logic low set opposite rotational directions.
Changes to this input do not take effect until the next STEP input
rising edge. Refer to Phase Current diagrams (Figures 10 to 17).
For DIR = LOW, currents change sequentially clockwise around
the circle. For DIR = HIGH, counterclockwise.
Internal PWM Current Control
Each full-bridge is controlled by a fixed off-time PWM current
control circuit that limits the load current to a desired value,
I_TRIP . Initially, a diagonal pair of source and sink FET outputs
are enabled and current flows through the motor winding and the
current sense resistor, R_Sx. When the voltage across R_Sx equals
the DAC output voltage, the current sense comparator resets the
PWM latch. The latch then turns off either the source FET (when
in Slow decay mode) or the sink and source FETs (when in Mixed
decay mode).
The maximum value of current limiting is set by the selection of
R_Sx and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
I_TripMAX (A), which is set by
× ^ITripMAX ^{= V}REF ^{/ ( 8 R}S⁾
where R_S is the resistance of the sense resistor (Ω) and V_REF is
the input voltage on the REF pin (V).
ROSC
t_BLANK ≈ 1 µs
The configuration of the ROSC terminal determines both the
method of current control as well as the fixed off-time (t_OFF).
ROSC
GND
Resistor to
GND
Pulled Up to
> 3 V Supply
Decay Mode
APFD
(Adaptive Percent Fast Decay
Mode)
Slow Decay Rising Current Steps
Mixed Decay Falling Current Steps
Slow Decay Rising Current Steps
Mixed Decay Falling Current Steps
t_OFF
16 µs
ROSC/825 (µs)
30 µs
Charge Pump (CP1 and CP2)
The charge pump is used to generate a gate supply greater than
that of VBB for driving the source-side FET gates. A 0.1 µF
ceramic capacitor, should be connected between CP1 and CP2. In
addition, a 0.1 µF ceramic capacitor is required between VCP and
VBB, to act as a reservoir for operating the high‑side FET gates.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
Enable Input (ENABLE)
The DAC output reduces the V_REF output to the current sense
comparator in precise steps, such that
× ^Itrip ^{= (%I}TripMAX ^{/ 100) I}TripMAX
(See table 2 for %I_TripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
This input turns on or off all of the FET outputs. When set to a
logic high, the outputs are disabled. When set to a logic low, the
internal control enables the outputs as required. The translator
inputs STEP, DIR, and MSx, as well as the internal sequencing
logic, all remain active, independent of the ¯E¯¯N ¯¯A ¯ ¯B¯¯L¯ ¯E¯ input state.
Sleep Mode (SLEEP)
To minimize power consumption when the motor is not in use,
SLEEP disables much of the internal circuitry including the
Allegro MicroSystems, LLC
12
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com