A1128LLTTR-T Datasheet, PDF(11/20 Page) Allegro MicroSystems – Highly Programmable Hall-Effect Switch

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

A1128LLTTR-T Datasheet, PDF (11/20 Pages) Allegro MicroSystems – Highly Programmable Hall-Effect Switch

◁

A1128

Highly Programmable Hall-Effect Switch

The four BOP selecting virtual registers allow the programmer

to adjust the BOP parameter for use in north or south magnetic

fields. In addition, values can be traversed from low to high, or

from high to low. Figure 12 shows the relationship between the

BOP parameter and the different Try mode registers. Note: See the

Output Polarity section for information about setting the POL bit

before using Try mode.

The FALL and POL fields are in the same register (FALL is

bits 1:0, and POL is bit 2). Therefore, in Try mode both can be

programmed simultaneously by adding the codes for the two

parameters, and send the sum as the code. For example, sending

code 7 (111) sets FALL to 3 (x11) and sets POL (1xx).

Blow Mode

After the required code is determined for a given parameter, its

value can be set permanently by blowing individual fuses in the

appropriate register bit field. Blowing is accomplished by select-

ing the register and mode selection key, followed by the appro-

priate bit field address, and ending the sequence with a Blow

pulse. The Blow mode selection key is a sequence of eleven VPM

pulses followed by one VPH pulse. The Blow pulse consists of a

VPH pulse of sufficient duration, tBLOW , to permanently set an

addressed bit by blowing a fuse internal to the device. The device

power must be cycled after each individual fuse is blown.

Due to power requirements, a 0.1 Î¼F blowing capacitor, CBLOW ,

must be mounted between the VCC pin and the GND pin dur-

ing programming, to ensure enough current is available to blow

fuses. If programming in the application, CBYPASS (see figure 1)

can serve the same purpose.

The fuse for each bit in the bit field must be blown individually.

The A1128 built-in circuitry allows only one fuse at a time to be

blown. During Blow mode, the bit field can be considered a âone-

hotâ shift register. Table 2 illustrates how to relate the number of

VPM pulses to the binary and decimal value for Blow mode bit

field addressing. It should be noted that the simple relationship

between the number of VPM pulses and the required code is:

2n = Code,

where n is the number of VPM pulses, and the bit field has an ini-

tial state of decimal code 1 (binary 00000001). To correctly blow

the required fuses, the code representing the required parameter

value must be translated to a binary number. For example, as

shown in figure 7, decimal code 5 is equivalent to the binary

number 101. Therefore bit 2 must be addressed and blown, the

device power supply cycled, and then bit 0 must be addressed

and blown. The order of blowing bits, however, is not impor-

tant. Blowing bit 0 first, and then bit 2 is acceptable. A complete

example is shown in figure 11.

Note: After blowing, the programming is not reversible, even

after cycling the supply power. Although a register bit field fuse

cannot be reset after it is blown, additional bits within the same

example, if bit 1 (binary 10) has been blown, it is still possible to

blow bit 0. The end result would be binary 11 (decimal code 3).

Locking the Device

After the required code for each parameter is programmed, the

device can be locked to prevent further programming of any

parameters. To do so, perform the following steps:

1. Ensure that the CBLOW capacitor is mounted.

2. Select the Output/Lock Bit register key.

3. Select Blow mode selection key.

4. Address bit 4 (10000) by sending four VPM pulses.

5. Send one Blow pulse, at IPP and SRBLOW, and sustain it for

tBLOW.

6. Delay for a tLOW interval, then power-down.

7. Optionally check all fuses.

Table 2. Blow Mode Bit Field Addressing

Quantity of

VPM Pulses

Binary

0000 0001

Decimal Equivalent

Code

0000 0010

0000 0100

0000 1000

0001 0000

0010 0000

0100 0000

1000 0000

128

Bit Field Selection

Address Code Format

Code in Binary

Fuse Blowing

Target Bits

(Decimal Equivalent)

Code 5

(Binary)

101

Bit 2

Bit 0

Fuse Blowing

Address Code Format

Code 4

Code 1

(Decimal Equivalents)

Figure 7. Example of code 5 broken into its binary components.

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

▷