A3948 Datasheet, PDF (10/13 Pages) Allegro MicroSystems – DMOS Full-Bridge PWM Motor Driver

3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
Terminal List
A3948SLB A3948SB
Terminal Name Terminal Description
(SOIC)
(DIP)
CP
Reservoir capacitor (typically 0.22 µF)
1
24
CP1 & CP2
The charge pump capacitor (typically 0.22 µF)
2&3
1&2
PHASE
Logic input for direction control (see also D15)
4
3
OSC
Logic-level oscillator (square wave) input
5
4
GROUND
Grounds
6, 7
5, 6, 7, 8*
LOGIC SUPPLY V_DD, the low voltage (typically 5 V) supply
ENABLE
Logic input for enable control (see also D14)
8
9
9
10
DATA
Logic-level input for serial interface
10
11
CLOCK
Logic input for serial port (data is entered on rising edge)
11
12
STROBE
Logic input for serial port (active on rising edge)
12
13
REF
V_REF, the load current reference input volt. (see also D16)
13
14
MODE
Logic input for PWM mode control (see also D17)
14
15
NO CONNECT No (Internal) Connection
15
—
OUT_A
SENSE
One of two DMOS bridge outputs to the motor
Sense resistor
16
16
17
17
GROUND
Grounds
18, 19
18, 19*
LOAD SUPPLY
OUT_B
NO CONNECT
V_BB, the high-current, 20 V to 50 V, motor supply
One of two DMOS bridge outputs to the motor
No (Internal) connection
20
20
21
21
22
—
RANGE
V_REG
Logic Input for V_REF range control (see also D16)
Regulator decoupling capacitor (typically 0.22 µF)
23
22
24
23
* For the A3948SB DIP only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18,
and 19) and the grounds at pins 5 and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally.
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