ATS667LSG Datasheet, PDF (1/14 Pages) Allegro MicroSystems – True Zero-Speed, High Accuracy Gear Tooth Sensor IC

ATS667LSG
True Zero-Speed, High Accuracy Gear Tooth Sensor IC
Features and Benefits
▪ Optimized robustness against magnetic offset variation
▪ Small signal lockout for immunity against vibration
▪ Tight duty cycle and timing accuracy over full operating
temperature range
▪ True zero-speed operation
▪ Air gap independent switchpoints
▪ Large operating air gaps achieved through use of gain
adjust and offset adjust circuitry
▪ Defined power-on state (POS)
▪ Wide operating voltage range
▪ Digital output representing target profile
▪ Single chip sensing IC for high reliability
▪ Small mechanical size
▪ Optimized Hall IC magnetic system
▪ Fast start-up
▪ Undervoltage lockout (UVLO)
Package: 4-pin SIP (suffix SG)
Description
TheATS667 is a true zero-speed gear tooth sensor IC consisting
of an optimized Hall IC-rare earth pellet configuration in a
single overmolded package. The unique IC and package design
provides a user-friendly solution for digital gear tooth sensing
applications. This small package can be easily assembled and
used in conjunction with gears of various shapes and sizes.
The device incorporates a dual element Hall IC that switches
in response to differential magnetic signals created by a ferro-
magnetic target. The IC contains a sophisticated compensating
circuit designed to eliminate the detrimental effects of magnet
and system offsets. Digital processing of the analog signal
provides zero-speed performance independent of air gap and
also dynamic adaptation of device performance to the typical
operating conditions found in automotive applications (reduced
vibration sensitivity). High-resolution peak detecting DACs
are used to set the adaptive switching thresholds of the device.
Hysteresis in the thresholds reduces the negative effects of any
anomalies in the magnetic signal associated with the targets
used in many automotive applications.
The ATS667 is optimized for transmission applications. It is
available in a lead (Pb) free 4-pin SIP package with a 100%
matte tin plated leadframe.
Not to scale
VCC
Functional Block Diagram
Voltage
Regulator
Hall
Amp
Offset
Adjust
Automatic
Gain
Control
V_PROC
PDAC
NDAC
PThresh
Reference
Generator
NThresh
Threshold
Comparator
Threshold
Logic
TEST
ATS667-DS, Rev. 2
GND
Current
Limit
Output
Transistor
VOUT