A6818 Datasheet, PDF (1/7 Pages) Allegro MicroSystems – Controlled output slew rate

A6818
DABiC-IV 32-Bit Serial Input
Latched Source Driver
Features and Benefits
▪ Controlled output slew rate
▪ 60 V minimum output break down
▪ PNP active pull-downs
▪ Low-power CMOS logic and latches
▪ High-speed data storage
▪ High data-input rate
▪ Low output-saturation voltages
▪ Improved replacements for SN75518N, SN75518NF,
UCN5818x, and UCQ5818x
Package: 44 pin PLCC (suffix EP)
Description
The A6818 device combines a 32-bit CMOS shift register,
accompanying data latches and control circuitry, with bipolar
sourcing outputs and PNP active pull-downs. Designed
primarily to drive vacuum-fluorescent displays, the 60 V and
–40 mA output ratings also allow this device to be used in
many other peripheral power driver applications. The A6818
features an increased data-input rate (compared with the older
UCN/UCQ5818x) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data-input rates are up to 33 MHz.
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. Similar devices
are available as the A6810 (10-bit) and A6812 (20-bit).
The A6818 output source drivers are NPN Darlingtons,
capable of sourcing up to 40 mA. The controlled output slew
rate reduces electromagnetic noise, which is an important
consideration in systems that include telecommunications
and/or microprocessors and to meet government emissions
Not to scale
Continued on the next page…
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
Functional Block Diagram
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V _DD
LOGIC
SUPPLY
SERIAL
DATA OUT
MOS
BIPOLAR
V_BB
LOAD
SUPPLY
GROUND
26182.128F
OUT ₁ OUT ₂ OUT ₃
OUT _N
Dwg. FP-013-1