A6800 Datasheet, PDF (1/12 Pages) Allegro MicroSystems – DABiC-5 Latched Sink Drivers

A6800/A6801
DABiC-5 Latched Sink Drivers
A6800SA
A6800SL
A6801SA
A6801SEP
A6801SLW
ABSOLUTE MAXIMUM RATINGS
Output Voltage, V_CE............................................50 V
Supply Voltage, V_DD .............................................7 V
Input Voltage Range, V_IN ..............–0.3 V toV_DD+0.3 V
Continuous Collector Current, I_C........................ 600 mA
Package Power Dissipation, P_D, see Allowable Power
Disspation chart, page 5
Operating Temperature Range
Ambient Temperature, T_A ............–20°C to +85°C
Storage Temperature, T_S ..........–55°C to +150°C
Caution: CMOS devices have input-static protection,
but are susceptible to damage when exposed to
extremely high static-electrical charges.
The A6800 and A6801 latched-input BiMOS ICs merge high-current,
high-voltage outputs with CMOS logic. The CMOS input section con-
sists of 4 or 8 data (‘D’ type) latches with associated common CLEAR,
STROBE, and OUTPUT ENABLE circuitry. The power outputs are
bipolar NPN Darlingtons. This merged technology provides versatile,
flexible interface. These BiMOS power interface ICs greatly benefit the
simplification of computer or microprocessor I/O. The A6800 ICs each
contain four latched drivers. A6801 ICs contain eight latched drivers.
The CMOS inputs are compatible with standard CMOS circuits. TTL
circuits may mandate the addition of input pull-up resistors. The bipolar
Darlington outputs are suitable for directly driving many peripheral/
power loads: relays, lamps, solenoids, small dc motors, etc.
All devices have open-collector outputs and integral diodes for induc-
tive load transient suppression. The output transistors are capable of
sinking 600 mA and will withstand at least 50 V in the OFF state.
Because of limitations on package power dissipation, the simultaneous
operation of all drivers at maximum rated current can only be accom-
plished by a reduction in duty cycle. Outputs may be paralleled for
higher load current capability.
The A6800SA is furnished in a standard 14-pin DIP; the A6800SL and
A6801SLW in surface-mountable SOICs; the A6801SA in a 22-pin
DIP with 0.400” (10.16 mm) row centers; the A6801SEP in a 28-lead
PLCC. These devices are lead (Pb) free, with 100% matte tin plated
leadframes.
FEATURES
„ 3.3 V to 5 V logic supply range
„
„ To 10 MHz data input rate
„
„ High-voltage, high-current outputs „
„ Darlington current-sink outputs, with ^„
improved low-saturation voltages
CMOS, TTL compatible inputs
Output transient protection
Internal pull-down resistors
Low-power CMOS latches
APPLICATIONS
„ Relays
„ Lamps
„ Solenoids
„ Small dc motors
Use the following complete part numbers when ordering:
Part Number
Pins
Package
A6800SA-T
14
DIP
A6800SL-T
14
SOIC
A6801SA-T
22
DIP
A6801SEP-T
28
PLCC
A6801SLW-T
24
SOIC