A4986_12 Datasheet, PDF (1/17 Pages) Allegro MicroSystems – DMOS Dual Full-Bridge PWM Motor Driver With Overcurrent Protection

A4986
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
Features and Benefits
▪ Low R_DS(ON) outputs
▪ Internal mixed current decay mode
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO
▪ Crossover-current protection
▪ 3.3 and 5 V compatible logic supply
▪ Thin profile QFN and TSSOP packages
▪ Thermal shutdown circuitry
▪ Short-to-ground protection
▪ Shorted load protection
▪ Low current Sleep mode, < 10 μA
Packages:
24-contact QFN
4 mm × 4 mm × 0.75 mm
(ES package)
Approximate size
24-pin TSSOP
with exposed thermal pad
(LP Package)
Description
The A4986 is a dual DMOS full-bridge stepper motor driver
with parallel input communication and overcurrent protection.
Each full-bridge output is rated up to 35 V and ±2 A.
The A4986 includes fixed off-time pulse width modulation
(PWM) current regulators, along with 2- bit nonlinear DACs
(digital-to-analog converters) that allow stepper motors to be
controlled in full, half, and quarter steps. The PWM current
regulator uses the Allegro^® patented mixed decay mode for
reduced audible motor noise, increased step accuracy, and
reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
The outputs are protected from shorted load and short-to-
ground events, which protect the driver and associated circuitry
from thermal damage or flare-ups. Other protection features
include thermal shutdown with hysteresis, undervoltage lockout
(UVLO) and crossover current protection. Special power-up
sequencing is not required.
The A4986 is supplied in a 24-contact QFN package (ES), and
a 24-pin TSSOP package (LP) with an overall package height
of ≤1.2 mm. Both packages have exposed pads for enhanced
thermal dissipation, and are lead (Pb) free (suffix –T), with
100% matte tin plated leadframes.
Typical Application Diagram
Microcontroller or
Controller Logic
V_DD
0.22 μF
0.1 μF
0.1 μF
0.22 μF
VREG ROSC CP1
VDD
CP2
VCP _VBB1
VBB2
SLEEP
IN01
IN02
PH1
IN11
IN12
PH2
VREF
A4986
OUT1A
OUT1B
SENSE1
GND
OUT2A
GND
OUT2B
SENSE2
100 μF
4986-DS, Rev. 4