A3950_06 Datasheet, PDF (1/12 Pages) Allegro MicroSystems – DMOS Full-Bridge Motor Driver

A3950
DMOS Full-Bridge Motor Driver
Features and Benefits
▪ Low R_DS(on) outputs
▪ Overcurrent protection
▪ Motor lead short-to-supply protection
▪ Short-to-ground protection
▪ Sleep function
▪ Synchronous rectification
▪ Diagnostic output
▪ Internal undervoltage lockout (UVLO)
▪ Crossover-current protection
Packages:
Package LP, 16 pin TSSOP
with Exposed Thermal Pad
Package EU, 16 pin QFN
with Exposed Thermal Pad
Description
Designed for PWM (pulse width modulated) control of dc
motors, the A3950 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM control signals. Internal synchronous rectification
control circuitry is provided to lower power dissipation during
PWM operation.
Internal circuit protection includes motor lead short-to-
supply / short-to-ground, thermal shutdown with hysteresis,
undervoltage monitoring of V_BB and V_CP, and crossover-current
protection.
The A3950 is supplied in a thin profile (<1.2 mm overall height)
16 pin TSSOP package (LP), and a very thin (0.75 mm nominal
height) QFN package. Both packages provide an exposed pad
for enhanced thermal dissipation, and are lead (Pb) free with
100% matte tin leadframe plating.
Approximate Scale 1:1
Typical Application Diagrams
V_DD
5 kΩ
0.22 μF
25 V
V_BB
0.1 μF
50 V
PHASE
GND
GND
SLEEP
ENABLE
CP2
A3950
EU Package ^CP1
OUTB
0.1 μF
50 V
100 μF
50 V
0.1 μF
50 V
Package EU
V_DD
5 kΩ
NFAULT
NC
MODE
VREG
PHASE
VCP
GND
SLEEP
A3950
GND
LP Package CP2
ENABLE
CP1
OUTA
OUTB
SENSE
VBB
V_BB
0.22 μF
25 V
0.1 μF
50 V
0.1 μF
50 V
100 μF
50 V
0.1 μF
50 V
Package LP
A3950DS, Rev. 4