AK6510C_05 Datasheet, PDF (9/18 Pages) Asahi Kasei Microsystems – SPI bus 64Kbit Serial CMOS EEPROM

ASAHI KASEI
[AK6514C]
WRITE (WRITE SEQUENCE)
WRITE instruction can start the WRITE function to the memory cell array.
After CS pin changes high to low, op-code, address and data are input from SI pin. After the
instruction input, the internal programming cycle starts when CS pin changes low to high. After the
instructions are inputted, CS pin should change low to high after the last data bit (D0) inputs and
before next SCK clock rises. Write function can start only at this timing.
AK6514C can indicate the BUSY status by using RDSR instruction and READ the RDY bit (Bit0) in
the status register. RDY is "1" indicates AK6514C is in the programming cycle, and RDY is "0"
indicates AK6514C is in the READY status. AK6514C outputs the "FF" when RDSR instruction
executes during the programming cycle. Only RDSR instruction can be accepted during
programming cycle.
AK6514C has Page Write mode, which can write the data within 64 bytes with one programming
cycle. The input data sent to the shift register within 64 bytes. If the number of bytes exceeded
64, the address counter rolls over to the first address of the page.
Internal programming cycle starts after CS pin changes low to high.
After WRITE instruction, AK6514C changes to Write Disable status automatically. AK6514C needs
WREN instruction before every WRITE instruction. When WRITE instruction is done while
AK6514C is in Write Disable status, WRITE instructions are ignored and AK6514C becomes
standby status after CS changes to high. AK6514C can accept the next instruction after CS
becomes low.
WRITE instruction cannot write the data into the address of the protected block.
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13
0 0 0 0 X 0 1 0 X X A13 A12 A11 A10
Hi-Z
22 23 24 25
30 31
Data(n)
A1 A0 D7 D6
D1 D0
CS
SCK
SI
SO
32 33 34 35 36 37 38 39 40
Data(n+1)
D7 D6 D5 D4 D3 D2 D1 D0 D7
Hi-Z
Data(n+63)
D0 D7 D6 D5 D4 D3 D2 D1 D0
X = don’t care
WRITE
DAP04E-00
-9-
2005/03