AK4635 Datasheet, PDF (9/81 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP

[AK4635]
0.345x AVDD(max)@MGAIN3-0 bits = “1001”
When the signal larger than above value is input to MICP or MICN pin, ADC does not operate normally.
Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ)
Note 9. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)
Note 10. When a PLL reference clock is FCK pin in PLL Slave Mode, S/ (N+D) of MICÆADC is 75dB (typ), S/ (N+D)
of DACÆAOUT is 75dB (typ).
Note 11. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)@LOVL bit = “0”.
Note 12. The value after passing LPF (LPF : Passband is 20kHz or less, Stopband Attenuation@250kHz is –50dB or less)
Note 13. In case of measuring at between the SPP pin and SPN pin directly.
Note 14. Load impedance is total impedance of series resistance (R_series) and piezo speaker impedance at 1kHz in
Figure 48. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series
resistors should be connected at both SPP and SPN pins, respectively.
Note 15. Maximum input voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD
x Rin/20kΩ (typ).
Note 16. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 17. Input Voltage does not depend on AVDD voltage.
Note 18. Measurement point is A of Figure 2 and Figure 3 when Sag Compensation mode and DC Output mode.
Measurement point A
VIN
CLAMP
LPF
GCA
75Ω
-1dB ~ +10.5dB
+6dB ^VOTU
Step 0.5dB
75Ω
VSAG
Figure 2 Measurement Point (at DC Output)
Measurement point A
VIN
CLAMP
LPF
GCA
C1 _75Ω
-1dB ~ +10.5dB
+6dB ^VOUT
Step 0.5dB
75Ω
VSAG C2
Figure 3. Measurement Point (Using Sag Compensation circuit)
Note 19. In the case of using Sag Compensation Circuit with 47μF+ 4.7μF and SAGC bit = “1”
Note 20. R1 and C2 compose of Low Pass Filter (LPF) in Figure 5. The cut off frequency of LPF is 10.6MHz at
C2=400pF.
VIN
CLAMP
LPF
GCA
-1dB ~ +10.5dB
Step 0.5dB
+6dB ^VOUT
VSAG
CL1
R1
75Ω
R2
75Ω
CL3
Figure 4. Load Capacitance C_L1 and C_L3 (at DC Output)
Rev. 0.6
2007/10
-9-