AK4317 Datasheet, PDF (9/19 Pages) Asahi Kasei Microsystems – 18BIT SCF DAC WITH ATT & MIXER

ASAHI KASEI
[AK4317]
„ System Clock
OPERATION OVERVIEW
The external clocks which are required to operate the AK4317 are MCLK, LRCK, BICK. The master
clock(MCLK)should be synchronized with LRCK but the phase is not critical. The MCLK is used to
operate the digital interpolation filter and the delta-sigma modulator. The frequency of MCLK is
determined by the sampling rate (LRCK) and CKS pin. Table 1 illustrates corresponding clock
frequencies. When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Refer to
Figure 1 .
All external clocks(MCLK,BICK,LRCK) should always be present whenever the AK4317 is in normal
operation mode(PD="H"). If these clocks are not provided, the AK4317 may draw excess current because
the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4317
should be in the power-down mode(PD="L"). After exiting reset at power-up etc., the AK4317 is in power-
down mode until MCLK and LRCK are input.
Clock
frequency
LRCK (fs)
8k∼50kHz
BICK
∼64fs
CKS="L"
MCLK
CKS="H"
256fs
384fs
Table 1 . System Clocks
Figure 1 . MCLK divider
„Audio Serial Interface Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Four serial data modes which are
compatible with AK4319 are supported and selected by the DIF0 and DIF1 pins as shown in Table 2 . In
all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK.
Mode 2 can be used for 16 MSB justified formats by zeroing the unused LSBs.
DIF1 DIF0
Mode
BICK Figure
0 0 0: 16bit LSB Justified
≥32fs Figure 2
0 1 1: 18bit LSB Justified
≥36fs Figure 2
1 0 2: 18bit MSB Justified
1 1 3: I²S Compatible
≥36fs Figure 3
≥36fs Figure 4
or 32fs
Table 2 . Serial Data Modes
0172-E-01
-9-
1997/5