AKD4145-A Datasheet, PDF (8/32 Pages) Asahi Kasei Microsystems – Evaluation board Rev.3 for AK4145

„ Setting of DIP SW
[AKD4145-A]
No.
Name
ON (“H”)
OFF (“L”)
Default
1
DIF0
H
2
DIF1
Output Audio Interface Format : refer to Table. 6
L
3
DIF2
H
4
OCKS1 Master Clock Frequency Setting : refer to Table. 7
L
5
CM0
Clock Mode Setting : refer to Table. 8
L
Table. 5 AK4114 Mode Setting
DIF2
0
0
0
0
1
1
DIF1
0
0
1
1
0
0
DIF0
DAUX
SDTO
0 24bit, Left justified
1 24bit, Left justified
0 24bit, Left justified
1 24bit, Left justified
0 24bit, Left justified
1 24bit, I²S
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I²S
Table. 6 AK4114 Audio Data Format
LRCK
H/L
H/L
H/L
H/L
H/L
L/H
BICK
64fs
64fs
64fs
64fs
64fs
64fs
OCKS1
MCKO1
L
256fs
H
512fs
Table. 7 AK4114 Master Clock Output Frequency
CM0
PLL
Clock Souce
SDTO
L
ON
PLL
RX
H
OFF
X’tal
DAUX
Table. 8 AK4114 Clock Operation Mode
<KM090003>
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2008/08