AK93C45CT Datasheet, PDF (8/16 Pages) Asahi Kasei Microsystems – 1K/2K/4Kbit Serial CMOS EEPROM

ASAHI KASEI
[AK93C45C/55C/65C]
WRAL
The write instruction is followed by 16 bits of data to be written into all address. After the last bit of
data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the
Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’. DO=logical "0"
indicates that programming is still in progress. DO=logical "1" indicates that the register at the
address specified in the instruction has been written with the new data pattern contained in the
instruction and the part is ready for a next instruction.
PE
CS
SK
DI
DO
0
1
2
3
4
5
6
7
8
9 10 11 12 13
0
1
0
0
0
1
0
0
0
0 D15 D14 D13 D12
Start Bit
Hi-Z
AK93C45C output a logic "1" (Ready status),
if previous instruction is W RITE, PAGE W RITE, W RAL.
WRAL (AK93C45C)
25 ^tCS
D0
Busy
Ready
tE/W
PE
CS
SK
DI
DO
0
1
2
3
4
5
6
7
8
9 10 11 12 13
0
1
0
0
0
1
0
0
0
0
0
0
Start Bit
Hi-Z
AK93C55C output a logic "1" (Ready status),
if previous instruction is W RITE, PAGE W RITE, W RAL.
WRAL (AK93C55C)
D15 D14
27 ^tCS
D0
Busy
Ready
tE/W
PE
CS
SK
DI
DO
0
1
2
3
4
5
6
7
8
9 10 11 12 13
0
1
0
0
0
1
0
0
0
0
0
0 D15 D14
Start Bit
Hi-Z
AK93C65C output a logic "1" (Ready status),
if previous instruction is W RITE, PAGE W RITE, W RAL.
WRAL (AK93C65C)
27 ^tCS
D0
Busy
Ready
tE/W
DAM06E-01
-8-
2005/10