AK9231 Datasheet, PDF (8/11 Pages) Asahi Kasei Microsystems – Dual 12-Bit 1MSPS SAR A/D Converter

[AK9231]
CSN
SCK
Hi-Z
SDO
tCSS
tCSD
0
tSCKL tSCKH
tDCD
D1
tDCH
D0
tCCZ
Hi-Z
VIH
VIL
VIH
VIL
50%VDD
Figure 3. Data Output Timing 2
9.2. Digital I/F
The AK9231 starts sampling input signals by a falling edge of the CSN pin and the AD conversion
process is initiated. Converted data is output from the SDOx pin (x= 0 or 1) during the conversion. After a
falling edge of the CSN pin, “0” data (4-bit) is output and then after four falling edges of SCK, AD
converted data (12-bit) is output from the SDOx pin in MSB first.
SDO data becomes Hi-Z on the 16th falling edge of SCK clock and the AD conversion ends. The
AK9231 enters the acquisition phase on the first rising edge of SCK after the 13th falling edge (“b” period
in Figure 4). The CSN pin can be set to “H” after the 16th falling edge of SCK clock. It is necessary not to
start the next conversion by pulling CSN low until the end of the quiet time (tq). Do not put the CSN pin to
“L” during the “tq” period after SDO data becomes Hi-Z. Normally, the CSN pin should not be set to “H”
until “b” timing in Figure 4.
The AD conversion stops and SDO data becomes Hi-Z if the CSN pin is put to “H” during the conversion.
At the same time, the AK9231 enters the acquisition phase. The CSN pin should be set to “L” after
waiting the acquisition time (minimum 325nsec) when re-starting the sampling.
The high level of the digital input is not limited to device VDD. For example, a 5.25V “H” level input is
accepted when the device supply voltage is 2.35V. It enables to connect other systems that have
different power supply level to the digital interface of the AK9231. Also this feature relaxes restriction on
power up sequencing. However, it should be noted that VOH and VOL are dependent on the device
VDD.
CSN
SCK
SDO
tCONV
tCS
U
b
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
tCSS
D11
SU ₀
tCSD
SU
1/throughput
tCCZ
D0
U
tq
Acquisition time
Figure 4. Digital I/F
014010771-E-00
-8-
2014/12