AK8137A Datasheet, PDF (8/11 Pages) Asahi Kasei Microsystems – Low Power Multiclock Generator with XO

AK8137A
Functional Description
Power On Reset
AK8137A has the POR(Power On Reset) circuit. In power up, the POR works and the register is set to the
initial value and all clock output becomes enable without glitch.
Note1) The assumption power start time to reach 90 % of VDD is within 20 ms.
Note2) The first register setting should be done after the 150 ms elapse after the power on.
VDD1/2/3
VD D*0.9
POR
(Internal signal)
XXX_Cp/REFOUT
XXX_Cn
Max:20ms
Min:150ms
Figure.4 Recommend Power On Reset Sequence
Power down Control
When the PDCLKN is “L”, CPU_Cp/Cn, USB_Cp/Cn and SATA_Cp/Cn clocks are forced to “L”. When it
is “H”, they are activated.
PDCLKN
XXX_Cp
XXX_Cn
< 300ns
PDCLKN
XXX_Cp
XXX_Cn
February-10
< 150ms
Figure.5 Power Down Sequence
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MS1109_E_02