AK5393VS Datasheet, PDF (8/18 Pages) Asahi Kasei Microsystems – Enhanced Dual Bit DS 96kHz 24-Bit ADC

ASAHI KASEI
[AK5393]
(Ta=25°C; VA=5.0V±5%; VD=3.0 ~ 5.25V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage Iout=-20µA
Low-Level Output Voltage Iout=20µA
Input Leakage Current
DC
Symbol
VIH
VIL
VOH
VOL
Iin
min
70%VD
-
VD-0.1
-
-
typ
max
-
-
-
30%VD
-
-
0.1
-
±10
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%; VD=3.0 ~ 5.25V; C_L=20pF)
Parameter
Symbol min
typ
Control Clock Frequency
Master Clock
256fs:
fCLK
0.256
12.288
Pulse width Low
tCLKL
29
Pulse width High
tCLKH
29
Serial Data Output Clock (SCLK)
fSLK
6.144
Channel Select Clock (LRCK)
fs
1
48
duty cycle
25
Serial Interface Timing
(Note 9)
Slave Mode(SMODE1="L")
SCLK Period
tSLK
144.7
SCLK Pulse width Low
tSLKL
65
Pulse width High
tSLKH
65
SCLK falling to LRCK Edge (Note 10)
tSLR
-45
LRCK Edge to SDATA MSB Valid
tDLR
SCLK falling to SDATA Valid
tDSS
SCLK falling to FSYNC Edge
tSF
-45
Master Mode(SMODE1="H")
SCLK Frequency (DFS ="L")
fSLK
128fs
SCLK Frequency (DFS ="H")
fSLK
64fs
duty cycle
50
FSYNC Frequency
fFSYNC
2fs
duty cycle
50
SCLK falling to LRCK Edge
tSLR
-20
LRCK Edge to FSYNC rising
tLRF
1
SCLK falling to SDATA Valid
tDSS
SCLK falling to FSYNC Edge
tSF
-20
Reset/Calibration timing
RST Pulse width
tRTW
150
RST falling to CAL rising
tRCR
RST rising to CAL falling (Note 11)
tRCF
8704
RST rising to SDATA Valid (Note 11)
tRTV
8960
Notes: 9.
10.
LRCK
SCLK " "
11. RST
LRCK
""
1-LRCK
(1/fs)
DFS ="H"
tRCF=17408,tRTV=17920
max
13.824
6.912
108
75
45
45
45
45
20
45
20
50
Units
V
V
V
V
µA
Units
MHz
ns
ns
MHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
Hz
Hz
%
Hz
%
ns
tslk
ns
ns
ns
ns
1/fs
1/fs
M0038-J-04
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