AK5358A_08 Datasheet, PDF (8/18 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ΔΣ ADC

[AK5358A]
SWITCHING CHARACTERISTICS
(Ta=-20°C ∼ 85°C; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 5.5V; C_L=20pF)
Parameter
Symbol
min
Master Clock Timing
512fs, 256fs Frequency
Pulse Width Low
Pulse Width High
768fs, 384fs Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
2.048
16
16
3.072
10.5
10.5
LRCK Frequency
Duty Cycle
Slave mode
Master mode
fs
8
45
Audio Interface Timing
Slave mode
SCLK Period
tSCK
160
SCLK Pulse Width Low
tSCKL
65
Pulse Width High
tSCKH
65
LRCK Edge to SCLK “↑”
(Note 12) tLRSH
30
SCLK “↑” to LRCK Edge
(Note 12) tSHLR
30
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
SCLK “↓” to SDTO
tSSD
Master mode
SCLK Frequency
fSCK
SCLK Duty
dSCK
SCLK “↓” to LRCK
tMSLR
−20
SCLK “↓” to SDTO
tSSD
−20
Reset Timing
PDN Pulse Width
(Note 13) ^tPD
150
PDN “↑” to SDTO valid at Slave Mode (Note 14) ^tPDV
PDN “↑” to SDTO valid at Master Mode (Note 14) ^tPDV
Note 12. SCLK rising edge must not occur at the same time as LRCK edge.
Note 13. The AK5358A can be reset by bringing the PDN pin = “L”.
Note 14. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
typ
50
64fs
50
4132
4129
max Units
24.576
36.864
96
55
MHz
ns
ns
MHz
ns
ns
kHz
%
%
ns
ns
ns
ns
ns
35
ns
35
ns
Hz
%
20
ns
35
ns
ns
1/fs
1/fs
MS0511-E-02
-8-
2008/01