AK5355VT Datasheet, PDF (8/20 Pages) Asahi Kasei Microsystems – Low Power 16bit ΔΣ ADC

ASAHI KASEI
[AK5355]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA, VD=2.1 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock (MCLK)
256fs: Frequency
Pulse Width Low
Pulse Width High
384fs: Frequency
Pulse Width Low
Pulse Width High
512fs: Frequency
Pulse Width Low
Pulse Width High
Channel Clock (LRCK) Frequency
Duty Cycle
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
duty
2.048
28
28
3.072
23
23
4.096
16
16
8
45
11.2896
16.9344
22.5792
44.1
Audio Interface Timing
BCLK Period
BCLK Pulse Width Low
Pulse Width High
BCLK “↓” to LRCK
LRCK Edge to SDTO (MSB)
BCLK “↓” to SDTO
tBLK
tBLKL
tBLKH
tBLR
tDLR
tDSS
312.5
130
130
-tBLKH+50
Reset / Initializing Timing
PDN Pulse Width
tPW
150
PDN “↑” to SDTO
(Note 8)
tPWV
4128
Note 8. This is the number of LRCK rising after the PDN pin is pulled high.
max
12.8
19.2
25.6
50
55
tBLKL-50
80
80
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
1/fs
MS0113-E-01
-8-
2005/01