AK5351 Datasheet, PDF (8/19 Pages) Asahi Kasei Microsystems – Enhanced Dual bit 20bit ADC

ASAHI KASEI
[AK5351]
„ SWITCHING CHARACTERISTICS
(Ta=25°C; VA,VD,VB=5.0V±10%; CL=20pF)
Parameter
Symbol
min
typ
max
Control Clock Frequency
Master Clock 256fs:
fCLK
2.048
12.288
13.824
Pulse width Low
tCLKL
30.0
Pulse width High
tCLKH
30.0
384fs:
fCLK
3.072
18.432
20.736
Pulse width Low
tCLKL
20.0
Pulse width High
tCLKH
20.0
Serial Data Output Clock
fSLK
3.072
6.912
Channel Select Clock(Sampling Frequency)
fs
8
48
54
Duty Cycle
25
75
Serial Interface Timing (Note 14 )
Slave Mode(SMODE1="L")
SCLK Period
tSLK
144.7
SCLK Pulse width Low
tSLKL
65
Pulse width High
tSLKH
65
SCLK Rising to LRCK Edge (Note 15 )
tSHLR
30
LRCK Edge to SCLK Rising (Note 15 )
tLRSH
30
LRCK Edge to SDATA MSB Valid
tDLR
50
SCLK Falling to SDATA Valid
tDSS
50
SCLK Rising to FSYNC Edge(Note 15 )
tSHF
30
FSYNC Edge to SCLK Rising(Note 15 )
tFSH
30
Master Mode(SMODE1="H")
SCLK Frequency
fSLK
64fs
Duty Cycle
50
FSYNC Frequency
fFSYNC
2fs
Duty Cycle
50
SCLK Falling to LRCK Edge
tSLR
-20
20
LRCK Edge to FSYNC Rising
tLRF
1
SCLK Falling to SDATA Valid
tDSS
50
SCLK Falling to FSYNC Edge
tSF
-20
20
Power down timing
PD Pulse width
tPDW
150
PD Rising to SDATA Valid (Note 16 )
tPDV
516
Note 14 : Refer to Serial Data Interface.
Note 15 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK.
Note 16 : The number of LRCK rising edges after PD brought high. The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer.
Unit
MHz
ns
ns
MHz
ns
ns
MHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
Hz
%
ns
tslk
ns
ns
ns
1/fs
0166-E-00
-8-
1997/4