AK4345 Datasheet, PDF (8/26 Pages) Asahi Kasei Microsystems – 100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC with DIT

[AK4345]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.7 ∼ 3.6V; C_L = 20pF)
Parameter
Symbol
min
typ
Master Clock Frequency
Half Speed Mode (512/768/1024/1536fs)
fCLK
4.096
Normal Speed Mode (256/384/512/768fs)
fCLK
2.048
Double Speed Mode (128/192/256/384fs)
fCLK
6.144
Duty Cycle
dCLK
40
LRCK Frequency
Half Speed Mode (DFS1-0 = “10”)
fsh
8
Normal Speed Mode (DFS1-0 = “00”)
fsn
8
Double Speed Mode (DFS1-0 = “01”)
fsd
48
Duty Cycle
dCLK
45
Audio Interface Timing
BICK Period
Half Speed Mode
tBCK
1/128fs
Normal Speed Mode
tBCK
1/128fs
Double Speed Mode
tBCK
1/64fs
BICK Pulse Width Low
tBCKL
70
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
tBCKH
70
(Note 11) tBLR
40
(Note 11) tLRB
40
SDTI Hold Time
tSDH
40
SDTI Setup Time
tSDS
40
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tCCK
200
tCCKL
80
tCCKH
80
tCDS
40
tCDH
40
tCSW
150
tCSS
150
tCSH
50
tDCD
tCCZ
Power-Down & Reset Timing
PDN Pulse Width
(Note 12) tPD
4
max
36.864
36.864
36.864
60
24
48
96
55
Units
MHz
MHz
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
ns
70
ns
ms/μF
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK4345 can be reset by bringing PDN pin = “L”.
The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4000× C.
When C = 4.7μF, tPD is 19ms(min).
The value of the capacitor (C) connected with VCOM pin should be 1μF ≤ C ≤ 10μF.
MS0635-E-00
-8-
2007/06