AK4141EQ Datasheet, PDF (8/32 Pages) Asahi Kasei Microsystems – Evaluation board Rev.2 for AK4141

[AKD4141-A]
„ Setting of DIP SW
(1). Setting of SW1 (AK4141)
SW1
No.
1
2
3
4
5
6
7
8
Name
IIS
4M50
4M51
4M52
6M5
MSN
CAD0
CAD1
ON (“H”)
OFF (“L”)
Audio Data Format Select Pin. ORed with ODIF bit, ORed with IDIF0 bit.
“L”: 24 bit Left Justified if IDIF0 bit = “0” (default).
“H”: 24/16 bit IIS.
Decoder Standard Preference Control 0 for 4.5MHz carrier.
4M5 [2:0] pin
“LLL”: PAL (Chroma Carrier)
“LLH”: M-Korea
“LHL”: EIAJ
“LHH”: Reserved
“HLL”: FM-Stereo Radio EU
“HLH”: FM-Stereo Radio EU
“HHL”: FM-Stereo Radio EU
“HHH”: FM-Stereo Radio US
This Pin is internally XORed with 4M5[2-0] bit (default = “011”).
Decoder Standard Preference Control for 6.5MHz carrier.
“L”: SECAM L NICAM
“H”: D/K1, D/K2, D/K3 or D/K NICAM
This Pin is internally XORed with 6M5 bit (default = “0”).
Master Mode Select Pin. ORed with CKS [1:0] bits.
“L”: Slave mode if CKS [2:0] bits = “000” (default).
“H”: Master mode of MCLK=256fs if CKS2 bit = “0” (default).
Chip Address 0 pin. Should match CAD0 bit in IIC first byte.
Chip Address 1 pin. Should match CAD1 bit in IIC first byte.
Table 4. SW1 Setting
Default
L
L
L
L
L
L
L
L
(2). Setting of SW4 (DIR: AK4114)
SW4
No.
1
2
3
4
5
6
7
Name
DIF2
DIF1
DIF0
CM1
CM0
OCKS1
OCKS0
ON (“H”)
OFF (“L”)
AK4114 Output Audio Interface Format Setting
refer to Table 6.
AK4114 Clock Mode Setting
Fixed to “L”.
AK4114 Master Clock Frequency Setting
refer to Table 7
Table 5. SW4 Setting
Default
H
L
L
L
L
H
L
Mode
0
1
2
3
4
5
6
7
DIF2
pin
L
L
L
L
H
H
H
H
DIF1 DIF0
pin pin
SDTO Format
LRCK
I/O
BICK
I/O
L L 16bit, Right justified H/L O 64fs O
L H 18bit, Right justified H/L O 64fs O
H L 20bit, Right justified H/L O 64fs O
H H 24bit, Right justified H/L O 64fs O
L L 24bit, Left justified H/L O 64fs O
L
H 24bit, I²S Compatible L/H O
64fs
O
H L 24bit, Left justified H/L I 64-128fs I
H H 24bit, I²S Compatible L/H I 64-128fs I
Table 6. AK4114 Output Audio Interface Format Setting
(Default)
<KM088102>
-8-
2007/11