AK8132A Datasheet, PDF (7/11 Pages) Asahi Kasei Microsystems – Multi Clock Generator

[AK8132A]
ｼﾞｯﾀの定義
1. Cycle to cycle jitter: The variation in cycle time of a single between adjacent cycles, over a random sample of
adjacent cycle pairs.
CLK1
CLK2
t_{cycle n}
t_{cycle n+1}
1/2VDD
CCJ = | t_cyclen - t_cyclen+1 | : where t_{cycle n} and t_cyclen+1 are any two adjacent cycles measured on controlled
edges.
2. Period jitter: The deviation in cycle time of a signal with respect to the ideal period over a random
sample of cycles. pairs.
CLK1
CLK2
t_{cycle n}
1/2VDD
PJ = t_cyclen - 1 / f0 : where fo is the nominal output frequency and tcycle n is any cycle within the
sample measured on controlled edges
MS1093-J-02
-7-
2010/01