AK4646_11 Datasheet, PDF (65/81 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/SPK-AMP

[AK4646]
SYSTEM DESIGN
Figure 37 shows the system connection diagram for the AK4646. An evaluation board [AKD4646] is available which
demonstrates the optimum layout, power supply arrangements and measurement results.
Sp eak er
Power Supply ^10u
2.2 ∼ 3.6V
ZD2
ZD 1
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2: ≥10Ω
ZD1, ZD2: Requi red
Line Out
Mono In
External MIC
Internal MIC
25 NC
20 0
1u
26 ROUT
20 0
1u
27 LOUT
28 MIN
29 RIN2
30 LIN2
31 LIN1
32 RIN1
AK4646
Top View
DVSS 16
DVDD 15
BICK 14
LRCK 13
SDTO 12
SDTI 11
CDTIO 10
CCLK 9
0 .1u
DSP
μP
Cp
Analog Ground Digital Ground
Notes:
- AVSS, DVSS and SVSS of the AK4646 should be distributed separately from the ground of external
controllers.
- All digital input pins should not be left floating.
- When the AK4646 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK4646 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4.
- When piezo speaker is used, 2.2 ∼ 4.0V power should be supplied to SVDD and 10Ω or more series resistors
should be connected to both SPP and SPN pins, respectively.
- When the AK4646 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, around 100kΩ pull-up resistor should be connected to LRCK and BICK pins of the AK4646.
Figure 37. System Connection Diagram
MS0557-E-05
- 65 -
2011/01