AK93C45C Datasheet, PDF (6/16 Pages) Asahi Kasei Microsystems – 1K/2K/4Kbit Serial CMOS EEPROM

ASAHI KASEI
[AK93C45C/55C/65C]
PAGE WRITE
AK93C45C/55C/65C has Page Write mode, which can write the data within 4 words with one
programming cycle. The input data sent to the shift register within 4 words. After the last bit of
data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the
Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.
After the receipt of each word, the two lower order address pointer bits internally incremented by
one. The higher order six bits of the word address remains constant. When the highest address
is reached ”XXXX XX11”, the address counter rolls over to address ”XXXX XX00” allowing the page
write cycle to be continued indefinitely.
If AK93C45C/55C/65C is transmitted more than 4 words, the address counter will ”roll over” and the
previously written data will be overwritten. When AK93C45C/55C/65C is transmitted 6 words, fifth
word will be overwritten to first word, and sixth word will be overwritten to second word.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
PE
CS
SK
0 1 2 3 4 5 6 7 8 9 10 11 12
23 24 25
Data(n)
DI
0 1 1 1 A5 A4 A3 A2 A1 A0 D15 D14 D13
D2 D1 D0
DO
Hi-Z
AK93C45C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
PE
CS
SK
26 27
39 40 41
tCS
Data(n+1)
DI
D15 D14
D2 D1 D0 D15
Data(n+3)
D0 D15 D14
D2 D1 D0
DO
Hi-Z
Busy
tE/W
Ready
PAGE WRITE (AK93C45C)
DAM06E-01
-6-
2005/10