AK4552 Datasheet, PDF (6/15 Pages) Asahi Kasei Microsystems – 3V 96KHZ 24BIT CODEC

ASAHI KASEI
[AK4552]
(Ta=25°C; VA, VD=2.4 ∼ 4.0V; C_L=20pF)
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
LRCK Frequency
Normal Speed
Double Speed
Quad Speed
Duty Cycle
Serial Interface Timing
BCLK Period
Normal Speed
Double Speed
Quad Speed
BCLK Pulse Width Low
Pulse Width High
LRCK Edge to BCLK “↑”
BCLK “↑” to LRCK Edge
LRCK Edge to SDTO (MSB)
BCLK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Reset Timing
PDN Pulse Width
PDN “↑” to SDTO Valid (
( 9)
( 9)
10)
Symbol
fCLK
tCLKL
tCLKH
fsn
fsd
fsq
Duty
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tDLR
tDBS
tSDH
tSDS
tPW
tPWV
9.
10. PDN
LRCK
BCLK “↑”
LRCK
“↑”
min
2.048
10
10
8
50
100
45
1/96fsn
1/64fsd
1/64fsq
33
33
20
20
20
20
150
typ
2081
max
Units
38.4
MHz
ns
ns
50
kHz
100
kHz
200
kHz
55
%
ns
ns
ns
ns
ns
ns
ns
40
ns
40
ns
ns
ns
ns
1/fs
MS0055-J-01
-6-
2001/02