AK4631_1 Datasheet, PDF (55/69 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4631]
SYSTEM DESIGN
Figure 42 shows the system connection diagram. An evaluation board [AKD4631] is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
1µ
2.2k
C
0.22µ
R
20k
220
1µ
0.1µ
Analog Supply
2.6∼3.6V
2.2µ+
10µ ₊
0.1µ
0.1µ
Cp Rp
1 VCOM
2 AVSS
3 AVDD
4 VCOC
5 PDN
6 CSN
7 CCLK
10
Top View
MIN 21
SVSS 20
SVDD 19
SPN 18
0.1µ 10µ
+
R2
SPP 17 _{R1 ZD2}
MCKO 16
Analog Supply
2.6∼5.25V
Speaker
ZD1
MCKI 15
Dynamic SPK :
R1,R2 : Short
ZD1,ZD2 : Open
Peizo SPK :
R1,R2 : 10Ω
ZD1,ZD2 : Required
0.1µ
+ _10µ
DSP or µP
Figure 42. Typical Connection Diagram
Notes:
- AVSS, DVSS and SVSS of the AK4631 should be distributed separately from the ground of external
controllers.
- All digital input pins except pull-down pin should not be left floating.
- Value of R and C of BEEP pin should depend on system.
- When the AK4631 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK4631 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 42.
- Input resistance of AIN pin and Capacitance between MICOUT pin and AIN pin compose of HPF. When the
capacitance is 0.22µF, the cut off frequency is typ.72Hz(typ)(min. 48Hz, max. 145Hz).
Mode
0
1
2
3
4
5
6
7
12
13
Others
PLL3
bit
0
0
0
0
0
0
0
0
1
1
PLL2
bit
0
0
0
0
1
1
1
1
1
1
Others
PLL1 PLL0 PLL Reference
bit bit Clock Input Pin
Input
Frequency
Rp and Cp of
VCOC pin
Rp[Ω] Cp[F]
0
0
FCK pin
1fs
6.8k 220n
0
1
BICK pin
16fs
10k 4.7n
1
0
BICK pin
32fs
10k 4.7n
1
1
BICK pin
64fs
10k 4.7n
0
0
MCKI pin 11.2896MHz 10k 4.7n
0
1
MCKI pin 12.288MHz 10k 4.7n
1
0
MCKI pin
12MHz
10k 4.7n
1
1
MCKI pin
24MHz
10k 4.7n
0
0
MCKI pin
13.5MHz 10k 10n
0
1
MCKI pin
27MHz
10k 10n
N/A
Table 42. Setting of PLL Mode (*fs: Sampling Frequency)
PLL Lock
Time
(max)
160ms
2ms
2ms
2ms
40ms
40ms
40ms
40ms
40ms
40ms
Default
MS0317-E-01
- 55 -
2004/11