AKD4631-VN Datasheet, PDF (5/44 Pages) Asahi Kasei Microsystems – 16bit mono CODEC with MIC/SPK amplifier.

ASAHI KASEI
[AKD4631-VN]
(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK
pin)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4631VN should be set to “1”. JP6 (MCKI) should be open.
b) Set up jumper pins of BICK clock
When an external clock through a RCA connector J8 (EXT/BICK) is supplied, select EXT on JP19
(MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to match the
output impedance of the clock generator.
JP17
XTE
JP21
MCLK_SEL
JP20
BICK
JP27
BICK
JP29
BICK_INV
XTL DIR EXT
INV THR DIR ADC INV THR
In this evaluation mode, the selected clock from JP21 (MCLK_SEL) is supplied to a divider (U3: 74VHC4040),
BICK and FCK clocks are generated by the divider. Input frequency of master clock is set up in turn “256fs”,
“512fs”, “1024fs” from left.
JP18
MKFS
JP18
MKFS
JP18
MKFS
256fs 512fs 1024fs MCKO 256fs 512fs1024fs MCKO 256fs 512fs1024fs MCKO
And input frequency of BICK is set up in turn “16fs”, “32fs”, “64fs” from left.
JP19
BICK_SEL
JP19
BICK_SEL
JP19
BICK_SEL
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
<KM077302>
-5-
2005/12