AK93C85A Datasheet, PDF (5/13 Pages) Asahi Kasei Microsystems – 16K / 32K / 64KBIT SERIAL CMOS EEPROM

ASAHI KASEI
[AK93C85A/95A/10A]
Write
The write instruction is followed by 16 bits of data to be written into the specified address.
AK93C85A : After the last bit of data is put on the DI pin, the CS pin must be brought low
before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming
cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns
(Tcs).
AK93C95A/10A : The self-timed programming cycle is initiated on the rising edge of the SK
clock as the last data bit (D0) is clocked in. The DO indicates the Busy/Ready status of the chip after the self-
timed programming cycle is initiated.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes
into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction
is given to the part.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the
address specified in the instruction has been written with the new data pattern contained in the instruction and
the part is ready for a next instruction.
DAM02E-01
-5-
1999/10