AK93C45B Datasheet, PDF (5/14 Pages) Asahi Kasei Microsystems – 1K / 2K / 4K / 8KBIT SERIAL CMOS EEPROM

ASAHI KASEI
[AK93C45B/55B/65B/75B]
Write
The write instruction is followed by 16 bits of data to be written into the specified address. After the last bit of
data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This
falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of
the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that programming
is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has
been written with the new data pattern contained in the instruction and the part is ready for a next instruction.
WRITE (AK93C45B)
*Address bit A7 becomes a “don’t care” for AK93C55B.
WRITE (AK93C55B/65B)
DAM04E-01
WRITE (AK93C75B)
-5-
1999/10