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AK5556 Datasheet, PDF (45/69 Pages) Asahi Kasei Microsystems – 6-Channel Differential 32-bit ADC | |||
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[AK5556]
MCLK
VIH
VIL
tMCB tBIM
BICK
VIH
VIL
Figure 54. Audio Interface Timing (Slave mode, TDM mode, MCLK=2ÃBICK)
MCLK
VIH
VIL
tMCB tBIM
BICK
VIH
VIL
Figure 55. Audio Interface Timing (Slave Mode, TDM Mode, MCLK=BICK)
[2] DSD Mode
DSD output is available only when the AK5556 is in Master mode.
The DCLK frequency can be selected from 64fs, 128fs and 256fs by setting the DSDSEL1-0 pins (bits).
The AK5556 enters Phase Modulation mode by setting PMOD pin = âHâ or PMOD bit = â1â. It does not
support Phase Modulation mode when the DCLK frequency is 256fs. DCKB bit controls DCLK polarity.
DCLK (64fs, 128fs, 256fs)
DCKB bit=â1â
DCLK (64fs, 128fs, 256fs)
DCKB bit=â0â
DSDOL, DSDOR D0
D1
Normal
D2
D3
DSDOL,DSDOR
Phase Modulation D0
D1
D1
D2
D2
D3
Figure 56. DSD Mode Timing
015099857-E-00
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2016/03
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