AKD4480-SB Datasheet, PDF (4/30 Pages) Asahi Kasei Microsystems – AK4480 Evaluation Board Rev.2

[AKD4480-SB]
The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 4.
OCKS1
OFF
ON
ON
OCKS0
MCLK Frequency
OFF
256fs @ fs=88.2/96kHz
OFF
512fs @ fs=32/44.1/48kHz
ON
128fs @ fs=176.4/192kHz
Table 4. MCLK Setting
(Default)
„ SW3 setting
[SW3] (PDN): Reset of AK4480. Select “H” during operation.
 External Analog Circuit
The differential output circuit and LPF is implemented on board. The differential outputs of AK4480 is buffered by
non-inverted circuit (2^nd order LPF, fc=106.4k, Q=0.698, G=+3.9dB). LPF adds differential outputs (1^st order LPF, fc=284k,
G=-0.84dB). LME49710NA is used for op-amp on this board that has low noise and high voltage torelance characteristics.
Analog signal is output via BNC connectors on the board. The output level is about 2.8Vrms (typ@VREF=5.0V) by BNC.
100u
AOUTL- ⁺
220
6.8n
220
LME49710NA
37
6.8n
2
+
-4
6
680
+ _10u
0.1u
10u
+
0.1u
100u
AOUTL+ ⁺
220
6.8n
220
LME49710NA
37
6.8n
2
+
-
4
6
680
+ _10u
0.1u
10u
+
0.1u
+15
-15
620
620
560
0.1u +^10u
1.0n
2 _- 4 ₆ ¹⁰⁰
3 ⁺⁷
Lch
1.0n LME49710NA
0.1u
+_10u
Figure 2. External Analog Filter
AKD4480-SB
Filter
40kHz (Double)
80kHz (quad)
Internal Filter
External LPF
Total
-0.3dB
-0.12dB
-0.42dB
-1dB
-1.3dB
-2.3dB
This table shows typical value.
Table 5. Frequency Responses
<KM097902>
4
2009/12