AKD4430-SA Datasheet, PDF (4/20 Pages) Asahi Kasei Microsystems – AK4430 Evaluation Board Rev.1

[AKD4430-SA]
„ Setting of DIP switch
[SW1]: AK4115 setting
No.
Pin
1 OCKS0
2 OCKS1
OFF (“L”)
ON (“H”)
AK4115’s Master Clock setting
Look Table 3
Table 2. SW1 setting
OCKS1
0
1
1
OCKS0
0/1
0
1
MCLK Frequency
256fs @ fs=96kHz
512fs @ fs=48kHz
128fs @ fs=192kHz
Default
„ Setting of SW2 switch
Table 3. MCLK clock setting
[SW2](PDN): Reset of AK4115. Keep “H” during normal operation.
Default の状態
L
H
KM101701
-4-
2010/04