AKD4424-SA Datasheet, PDF (4/22 Pages) Asahi Kasei Microsystems – AK4424 Evaluation Board Rev.1

[AKD4424-SA]





Setting of DIP switch
[SW1]: AK4115 setting
No.
Pin
1 OCKS1
2 OCKS0
OFF
ON
AK4115’s Master Clock setting
Look Table 3
Table 2. SW1 setting
OCKS1
0
1
1
OCKS0
0/1
0
1
MCLK Frequency
256fs @ fs=96kHz
512fs @ fs=48kHz
128fs @ fs=192kHz
Default
Table 3. MCLK clock setting
Setting of SW2 switch
[SW2](PDN): Reset of AK4115. Keep “H” during normal operation.
Default ͷঢ়ଶ
ON
OFF
KM092501





2008/03