AKD4421A-SA Datasheet, PDF (4/22 Pages) Asahi Kasei Microsystems – AK4421A Evaluation Board Rev.1

[AKD4421A-SA]





„ Setting of DIP switch
[SW1]: AK4115 setting
No.
Pin
1 OCKS1
2 OCKS0
OFF
ON
AK4115’s Master Clock setting
Look Table 3
Table 2. SW1 setting
OCKS1
0
1
1
OCKS0
0/1
0
1
MCLK Frequency
256fs @ fs=96kHz
512fs @ fs=48kHz
128fs @ fs=192kHz
Default
„ Setting of SW2 switch
Table 3. MCLK clock setting
[SW2](PDN): Reset of AK4115. Keep “H” during normal operation.
Default ͷঢ়ଶ
ON
OFF
KM098701

































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2009/04