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AKD4420-SC Datasheet, PDF (4/22 Pages) Asahi Kasei Microsystems – AK4420 Evaluation Board Rev.2 | |||
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[AKD4420-SC]
 Setting of DIP switch
[SW1]: AK4115 setting
No.
Pin
1 OCKS0
2 OCKS1
OFF (âLâ)
ON (âHâ)
AK4115âs Master Clock setting
Look Table 3
Table 2. SW1 setting
OCKS1
0
1
1
OCKS0
0/1
0
1
MCLK Frequency
256fs @ fs=96kHz
512fs @ fs=48kHz
128fs @ fs=192kHz
Default
 Setting of SW2 switch
Table 3. MCLK clock setting
[SW2](PDN): Reset of AK4115. Keep âHâ during normal operation.
Default Í·à§à¬¶
OFF
ON
KM091904
2009/07
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