AKD4388-SB Datasheet, PDF (4/26 Pages) Asahi Kasei Microsystems – 192kHz sampling 24Bit ΔΣ DAC

ASAHI KASEI
[AKD4388-SB]
„ DIP Switch setting
[SW1]: AK4388 setting
No.
Pin
1
SMUTE
2
P/S
3
ACKS
4
DIF0
SW1 OFF
SW1 ON
Soft Mute : “Disable”
Soft Mute : “Enable”
Always ON for Parallel Control mode only
Manual setting mode
Auto setting mode
Audio Data Formats Refer to Table7
Table 2. SW1 setting
Default
OFF
ON
ON
OFF
[SW2]: AK4388 setting
No.
Pin
1
-
2
-
3
DEM
4
DIF1
NC
NC
De-emphasis Control setting Refer to Table6
Audio Data Formats Refer to Table7
Table 3. SW2 setting
Default
OFF
OFF
OFF
ON
[SW3]: AK4113 setting
No.
Pin
1
OCKS1
2
OCKS0
OFF
ON
AK4113 Master Clock setting
Refer to Table 5.
Table 4. SW3 setting
Default
ON
OFF
The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 5.
OCKS1
0
1
1
OCKS0
0
0
1
MCLK Frequency
256fs @fs=88.2/96kHz
512fs @32/44.1/48kHz
128fs @176.4/192kHz
Table 5. MCLK Clock
Default
The digital de-emphasis filter is set by DEM pin as follows.
DEM SW
OFF
ON
DEM pin state De-emphasis Filter
1
ON
0
OFF
Table 6. De-emphasis Filter Control
Default
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-1 as shown in Table 7 can select four serial
data modes.
Mode
0
1
2
3
DIF1 SW
ON
ON
OFF
OFF
DIF0 SW
ON
OFF
ON
OFF
DIF1 pin state DIF0 pin state
SDTI Format
0
0
16bit LSB justified
0
1
24bit LSB justified
1
0
24bit MSB justified
1
1
16/24bit I²S Compatible
Table 7. Audio Data Formats
BICK
≥32fs
≥48fs
≥48fs
≥48fs or 32fs
Default
<KM083502>
4
2006/09