AKD4341-SB Datasheet, PDF (4/23 Pages) Asahi Kasei Microsystems – 192kHz sampling 24Bit ΔΣ DAC

ASAHI KASEI
[AKD4341-SB]
The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 4.
OCKS1
0
1
1
OCKS0
MCLK Frequency
0
256fs @fs=88.2/96kHz
0
512fs @ fs=32/44.1/48kHz
1
128fs @ fs=176.4/192kHz
Table 4. MCLK Clock
Default
„ Setting of SW3 (Setting of PDN of AK4341)
[SW3](PDN): Reset of AK4341. Select “H” during operation.
„ Setting of SW4 (Setting of SMUTE of AK4341)
[SW4](SMUTE): Soft-mute of AK4341. Soft-mute is executed during pushed.
„ Setting of jumper pin JP1 (Setting of GAIN of AK4341)
[JP1](GAIN): Output level of AOUTL/AOUTR pin of AK4341 can be selected by jumper pin JP1 (GAIN).
(For further details, please refer to datasheet of AK4341.)
GAIN GAIN
(JP1)
L
0dB (Default)
H
+6dB
Open
+12dB
Table 5. Setting of output level of AOUTL/AOUTR pin of AK4341
<KM087300>
4
2007/03