AKD4116 Datasheet, PDF (4/19 Pages) Asahi Kasei Microsystems – AK4116 Evaluation Board Rev.0

ASAHI KASEI
[AKD4116-B]
c. Set-up of Audio format
Please set up DIF2-0 bit.
Mode
0
1
2
3
4
5
6
7
DIF2
bit
0
0
0
0
1
1
1
1
DIF1
bit
0
0
1
1
0
0
1
1
DIF0
bit
0
1
0
1
0
1
0
1
DAUX
SDTO
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I²S
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I²S
Reserved
Table 3. Audio format
LRCK
I/O
H/L O
H/L O
H/L O
H/L O
H/L O
L/H O
Default
d. Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. It can be selected by CM1-0 bits.
CM1 bit CM0 bit (UNLOCK) PLL
X'tal
Clock source
SDTO
source
0
0
-
ON ON(Note 1)
PLL(RX)
RX Default
0
1
-
OFF
ON
X'tal
DAUX
1
0
0
ON
ON
PLL(RX)
RX
1
ON
ON
X'tal
DAUX
1
1
-
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 4. Clock Operation Mode Select
<KM077400>
-4-
2005/01