AKD4114-B Datasheet, PDF (4/23 Pages) Asahi Kasei Microsystems – AK4114 Evaluation Board Rev.0

ASAHI KASEI
[AKD4114-B]
b-2. Set-up of input/output of BICK and LRCK
Please select SW 3_7 (DIR_I/O) according to the setup of audio format of AK4114 (Refer to Table 7).
Audio format
SW3_7 (DIR_I/O)
Slave mode
0
Master mode
1
Table 6. Set-up of DIR_I/O
Default
c. Set-up of Audio format
It sets up by SW 1_2, SW 1_3 and SW1_4 in parallel mode. Please set up DIF2-0 bit in serial mode.
Mode
0
1
2
3
4
5
6
7
DIF2 pin
(SW1_4)
DIF2 bit
0
0
0
0
1
1
1
1
DIF1 pin
(SW1_3)
DIF1 bit
0
0
1
1
0
0
1
1
DIF0 pin
(SW1_2) DAUX
SDTO
DIF0 bit
0
24bit, Left 16bit, Right
justified
justified
1
24bit, Left 18bit, Right
justified
justified
0
24bit, Left 20bit, Right
justified
justified
1
24bit, Left 24bit, Right
justified
justified
0
24bit, Left
justified
24bit, Left
justified
1
24bit, I²S
24bit, I²S
0
24bit, Left
justified
24bit, Left
justified
1
24bit, I²S
24bit, I²S
Table 7. Audio format
LRCK
I/O
H/L O
H/L O
H/L O
H/L O
H/L O
L/H O
H/L I
L/H I
BICK
I/O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64-128fs I
64-128fs I
Default
d. Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_1 and
JP18. In serial mode, it can be selected by CM1-0 bits.
CM1 pin
CM0 pin (JP18)
(SW3_1)
(UNLOCK) PLL
X'tal
CM1 bit
CM0 bit
Clock
source
SDTO
source
0
0 (CM0)
-
ON ON(Note) PLL(RX)
RX
Default
0
1 (CDTO/CM0=H)
-
OFF
ON
X'tal
DAUX
1
0 (CM0)
0
ON
ON
PLL(RX)
RX
1
ON
ON
X'tal
DAUX
1
1 (CDTO/CM0=H)
-
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 8. Clock Operation Mode Select
<KM076602>
-4-
2005/12