AKD4112B-B Datasheet, PDF (4/25 Pages) Asahi Kasei Microsystems – 96kHz digital audio receiver.

ASAHI KASEI
[AKD4112B-B]
b-2. Set-up of BICK and LRCK input and output
Please select SW 3_7 (DIR_I/O) according to the setup of audio format of AK4112B (Refer to Table 7).
Output signal
SW3_7 (DIR_I/O)
Slave mode
0
Master mode
1
Table 7. DIR_I/O set-up
Default
c. Set-up of Audio data format
It sets up by SW 1_2, SW 1_3 and SW1_4 in parallel mode. Please set up DIF2-0 bit in serial mode.
Mode
0
DIF2 pin
(SW1_4)
DIF2 bit
0
1
0
2
0
3
0
4
1
5
1
6
1
7
1
DIF1 pin
(SW1_3)
DIF1 bit
0
0
1
1
0
0
1
1
DIF0 pin
(SW1_2)
DIF0 bit
0
1
0
1
0
1
0
1
DAUX
SDTO
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I²S
24bit, Left
justified
24bit, I²S
16bit, Right
justified
18bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I²S
24bit, Left
justified
24bit, I²S
Table 8. Audio data format
LRCK
I/O
H/L O
H/L O
H/L O
H/L O
H/L O
L/H O
H/L I
L/H I
BICK
I/O
64fs O
64fs O
64fs O
64fs O
64fs O
64fs O
64-
128fs
I
64-
128fs
I
Default
d. Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_1 and
JP18. In serial mode, it can be selected by CM1-0 bits.
CM1 pin
CM0 pin (JP18)
(SW3_1)
(UNLOCK) PLL
X'tal
CM1 bit
CM0 bit
Clock
source
SDTO
source
0
0 (CM0=“L”)
-
ON ON (Note) PLL (RX)
RX
Default
1
0
-
(CDTO/CM0=“H”)
OFF
ON
X'tal
DAUX
1
0 (CM0=“L”)
0
ON
ON
PLL (RX)
RX
1
ON
ON
X'tal
DAUX
1
1
-
(CDTO/CM0=“H”)
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 9. Clock Operation Mode Select
<KM080200>
-4-
2005/10